公开(公告)号：US20220158552A1

公开(公告)日：2022-05-19

申请号：US17494244

申请日：2021-10-05

Applicant: STMicroelectronics International N.V.

Inventor： Vikas RANA

IPC: H02M3/07 ,  H02M1/00 ,  G05F1/59

Abstract: The charge transfer transistors of a positive or negative charge pump are biased at their gate terminals with a control voltage that provides for an higher level of gate-to-source voltage in order to reduce switch resistance in passing a boosted (positive or negative) voltage to a voltage output of the charge pump. This control voltage is generated using a bootstrapping circuit whose polarity of operation (i.e., negative or positive) is opposite to a polarity (i.e., positive or negative) of the charge pump.

公开(公告)号：US20190393779A1

公开(公告)日：2019-12-26

申请号：US16563069

申请日：2019-09-06

Applicant: STMicroelectronics International N.V.

Inventor： Vikas RANA

IPC: H02M3/07 ,  H03K19/096 ,  G05F1/10

Abstract: A voltage doubler circuit supports operation in both a positive voltage boosting mode to positively boost voltage from a first node to a second node and a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuit is formed by transistors of a same conductivity type that share a common bulk that is not tied to a source of any of the voltage doubler circuit transistors. A bias generator circuit is coupled to receive a first voltage from the first node and second voltage from the second node. The bias generator circuit operates to apply a lower one of the first and second voltages to the common bulk.

公开(公告)号：US20220286048A1

公开(公告)日：2022-09-08

申请号：US17673033

申请日：2022-02-16

Applicant: STMicroelectronics International N.V.

Inventor： Vikas RANA

IPC: H02M3/07

Abstract: A charge pump circuit includes a boost capacitor driven by a first clock signal and a bootstrap capacitor driven by a second clock signal. The first and second clock signals have different duty cycles, with the duty cycle of the second clock signal being smaller than the duty cycle of the first clock signal. An input transistor is coupled between an input node and a boost node coupled to the boost capacitor. The control terminal of the input transistor is coupled to the bootstrap capacitor. A bootstrap transistor coupled between the boost node and the control terminal of the input transistor is driven by a logical inverse of the first clock signal.

公开(公告)号：US20220208279A1

公开(公告)日：2022-06-30

申请号：US17548096

申请日：2021-12-10

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Arpit VIJAYVERGIA ,  Vikas RANA

IPC: G11C16/28 ,  G11C16/04 ,  G11C16/24

Abstract: An integrated circuit includes a memory array and a memory read circuitry for reading data from the memory array. The memory read circuitry includes a leakage current compensation circuit. The leakage current compensation circuit senses the leakage current in a bitline of the memory array during a read operation and generates a leakage compensation current to offset the leakage current during the read operation.

公开(公告)号：US20220165339A1

公开(公告)日：2022-05-26

申请号：US17527031

申请日：2021-11-15

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Vikas RANA ,  Arpit VIJAYVERGIA

IPC: G11C16/30 ,  H02M3/07

Abstract: An integrated circuit includes a charge pump. The charge pump includes a plurality of charge pump stages and a plurality of switches. The switches can operated to selectively couple the charge pump stages in various arrangements of series and parallel connections based on a currently selected operational mode of the charge pump. The charge pump assists in performing read and write operations for a memory array of the integrated circuit.

公开(公告)号：US20200235659A1

公开(公告)日：2020-07-23

申请号：US16715209

申请日：2019-12-16

Applicant: STMicroelectronics International N.V.

Inventor： Vikas RANA ,  Shivam KALLA

IPC: H02M3/07 ,  G11C5/14 ,  G11C16/30

Abstract: A charge pump circuit generates a charge pump output signal at a first node and is enabled by a charge pump control signal. A diode has first and second terminals coupled to first and second nodes. A comparator has an inverting input coupled to the second node and a non-inverting input coupled to a third node, and causes generation of the charge pump control signal. A first current mirror produces a first current at the second node, and a second current mirror produces a second current (equal in magnitude to the first current) at the third node. The first terminal and second terminals may be a cathode and an anode. The first current mirror may be a current sink sinking a first current from the second node. The second current mirror may be current source sourcing a second current (equal in magnitude to the first current) to the third node.