公开(公告)号：US20190311675A1

公开(公告)日：2019-10-10

申请号：US16372296

申请日：2019-04-01

Applicant: Samsung Display Co., Ltd.

Inventor： Tae Hoon Yang ,  Ki Bum Kim ,  Jong Chan Lee ,  Woong Hee Jeong

IPC: G09G3/3233 ,  G09G3/3266 ,  G09G3/3283 ,  H01L27/32

Abstract: A pixel including a light emitting element, a first transistor connected between a first node and the light emitting element to control current flowing from a first power supply to a second power supply, a second transistor connected between a data line and the first transistor to be turned on by an ith first scan signal, a third transistor including a P-type TFT connected between the first transistor and the first node to be turned on by the ith first scan signal and, a fourth transistor including an N-type TFT connected between the first node and an initialization power supply line to be turned on by an i−1th scan signal, and a first connection line connected between the third and fourth transistors to electrically connect semiconductor patterns thereof, in which the first connection line is disposed on the third and fourth transistors and contacts the semiconductor patterns thereof.

公开(公告)号：US20190295472A1

公开(公告)日：2019-09-26

申请号：US16210379

申请日：2018-12-05

Applicant: Samsung Display Co., Ltd.

Inventor： Tae Hoon YANG ,  Ki Bum Kim ,  Jong Chan Lee ,  Woong Hee Jeong

IPC: G09G3/3266 ,  G09G3/3291 ,  G09G3/3233 ,  G09G3/3258 ,  H01L27/32

Abstract: A scan driver includes stage circuits, each including: a first circuit including a control terminal (CT) connected to a first node (N1), and connecting/disconnecting a previous scan line of a previous stage circuit to a second node (N2) based on a control signal (CS); a second circuit including a CT connected to a clock signal line, and connecting one of a first power voltage line (FPVL) and a second power voltage line (SPVL) to the N1 based on a CS; a third circuit including a CT connected to the N2, and connecting one of the N1 and the SPVL to a third node (N3) based on a CS; a fourth circuit including a CT connected to the N3, and connecting one of the FPVL and the SPVL to a current scan line based on a CS; and a first capacitor connecting the CT of the third circuit and the SPVL.