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公开(公告)号:US20180061865A1
公开(公告)日:2018-03-01
申请号:US15678503
申请日:2017-08-16
Inventor: Jae Heung Ha , Jong Woo Kim , Ji Young Moon , Min Ho Oh , Seung Jae Lee , Yoon Hyeung Cho , Young Cheol Joo , Hyeong Joon Kim , Eun-Kil Park , Sang Jin Han
IPC: H01L27/12 , H01L29/49 , H01L29/786
CPC classification number: H01L27/1225 , H01L29/4908 , H01L29/7869
Abstract: A thin film transistor array panel includes a substrate, a gate insulating layer, an interface layer, and a semiconductor layer. The gate insulating layer is disposed on the substrate. The interface layer is disposed on the gate insulating layer. The semiconductor layer is disposed on the interface layer. The interface layer includes a fluorinated silicon oxide. The semiconductor layer includes a p-type oxide semiconductor material.