公开(公告)号：US11620491B2

公开(公告)日：2023-04-04

申请号：US16842700

申请日：2020-04-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Lei Wang ,  Ilia Ovsiannikov

IPC: G06T9/00 ,  G06N3/063 ,  G06N3/04 ,  G06F17/16 ,  G06N3/08 ,  G06F17/15 ,  G06F9/30

Abstract: A processor includes a register, a non-zero weight value selector and a multiplier. The register holds a first group of weight values and a second group of weight values. Each group of weight values includes at least one weight value, and each weight value in the first group of weight values corresponding to a weight value in the second group of weight values. The non-zero weight value selector selects a non-zero weight value from a weight value in the first group of weight values or a non-zero weight value in the second group of weight values that corresponds to the weight value in the first group of weight values. The multiplier multiplies the selected non-zero weight value and an activation value that corresponds to the selected non-zero weight value to form an output product value.

公开(公告)号：US11551055B2

公开(公告)日：2023-01-10

申请号：US16842700

申请日：2020-04-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Lei Wang ,  Ilia Ovsiannikov

IPC: G06T9/00 ,  G06N3/063 ,  G06N3/04 ,  G06F17/16 ,  G06N3/08 ,  G06F17/15 ,  G06F9/30

Abstract: A processor includes a register, a non-zero weight value selector and a multiplier. The register holds a first group of weight values and a second group of weight values. Each group of weight values includes at least one weight value, and each weight value in the first group of weight values corresponding to a weight value in the second group of weight values. The non-zero weight value selector selects a non-zero weight value from a weight value in the first group of weight values or a non-zero weight value in the second group of weight values that corresponds to the weight value in the first group of weight values. The multiplier multiplies the selected non-zero weight value and an activation value that corresponds to the selected non-zero weight value to form an output product value.

公开(公告)号：US12086700B2

公开(公告)日：2024-09-10

申请号：US16552619

申请日：2019-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilia Ovsiannikov ,  Ali Shafiee Ardestani ,  Joseph H. Hassoun ,  Lei Wang ,  Sehwan Lee ,  JoonHo Song ,  Jun-Woo Jang ,  Yibing Michelle Wang ,  Yuecheng Li

IPC: G06N3/04 ,  G06F9/30 ,  G06F17/15 ,  G06F17/16 ,  G06N3/08 ,  G06T9/00

CPC classification number: G06N3/04 ,  G06F17/153 ,  G06F17/16 ,  G06N3/08 ,  G06T9/002 ,  G06F9/3001

Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.

公开(公告)号：US11783162B2

公开(公告)日：2023-10-10

申请号：US16552619

申请日：2019-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilia Ovsiannikov ,  Ali Shafiee Ardestani ,  Joseph H. Hassoun ,  Lei Wang ,  Sehwan Lee ,  JoonHo Song ,  Jun-Woo Jang ,  Yibing Michelle Wang ,  Yuecheng Li

IPC: G06N3/04 ,  G06F17/16 ,  G06F9/30 ,  G06N3/08 ,  G06F17/15 ,  G06T9/00

CPC classification number: G06N3/04 ,  G06F17/153 ,  G06F17/16 ,  G06N3/08 ,  G06T9/002 ,  G06F9/3001

Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.

公开(公告)号：US11671111B2

公开(公告)日：2023-06-06

申请号：US16842662

申请日：2020-04-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilia Ovsiannikov ,  Ali Shafiee Ardestani ,  Lei Wang ,  Joseph H. Hassoun

IPC: H04L5/02 ,  G06F9/38 ,  G06F9/30 ,  H03M7/30 ,  H03M7/40

CPC classification number: H03M7/3066 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3818 ,  G06F9/3851 ,  H03M7/40 ,  H03M7/6005 ,  H03M7/6011 ,  H03M7/6023 ,  H04L5/023

Abstract: A multichannel data packer includes a plurality of two-input multiplexers and a controller. The plurality of two-input multiplexers is arranged in 2N rows and N columns in which N is an integer greater than 1. Each input of a multiplexer in a first column receives a respective bit stream of 2N channels of bit streams. Each respective bit stream includes a bit-stream length based on data in the bit stream. The multiplexers in a last column output 2N channels of packed bit streams each having a same bit-stream length. The controller controls the plurality of multiplexers so that the multiplexers in the last column output the 2N channels of bit streams that each has the same bit-stream length.

公开(公告)号：US11579842B2

公开(公告)日：2023-02-14

申请号：US17151115

申请日：2021-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilia Ovsiannikov ,  Ali Shafiee Ardestani ,  Joseph Hassoun ,  Lei Wang

IPC: G06F7/487 ,  G06F7/523 ,  G06F9/30

Abstract: An N×N multiplier may include a N/2×N first multiplier, a N/2×N/2 second multiplier, and a N/2×N/2 third multiplier. The N×N multiplier receives two operands to multiply. The first, second and/or third multipliers are selectively disabled if an operand equals zero or has a small value. If the operands are both less than 2N/2, the second or the third multiplier are used to multiply the operands. If one operand is less than 2N/2 and the other operand is equal to or greater than 2N/2, the first multiplier is used or the second and third multipliers are used to multiply the operands. If both operands are equal to or greater than 2N/2, the first, second and third multipliers are used to multiply the operands.

公开(公告)号：US10963220B2

公开(公告)日：2021-03-30

申请号：US16276582

申请日：2019-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilia Ovsiannikov ,  Ali Shafiee Ardestani ,  Joseph Hassoun ,  Lei Wang

IPC: G06F7/487 ,  G06F9/30 ,  G06F7/523

Abstract: An N×N multiplier may include a N/2×N first multiplier, a N/2×N/2 second multiplier, and a N/2×N/2 third multiplier. The N×N multiplier receives two operands to multiply. The first, second and/or third multipliers are selectively disabled if an operand equals zero or has a small value. If the operands are both less than 2N/2, the second or the third multiplier are used to multiply the operands. If one operand is less than 2N/2 and the other operand is equal to or greater than 2N/2, the first multiplier is used or the second and third multipliers are used to multiply the operands. If both operands are equal to or greater than 2N/2, the first, second and third multipliers are used to multiply the operands.

公开(公告)号：US20200026979A1

公开(公告)日：2020-01-23

申请号：US16552850

申请日：2019-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilia Ovsiannikov ,  Ali Shafiee Ardestani ,  Joseph H. Hassoun ,  Lei Wang ,  Sehwan Lee ,  JoonHo Song ,  Jun-Woo Jang ,  Yibing Michelle Wang ,  Yuecheng Li

IPC: G06N3/04 ,  G06F17/16 ,  G06N3/08

Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.