公开(公告)号：US20240256828A1

公开(公告)日：2024-08-01

申请号：US18601739

申请日：2024-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilia Ovsiannikov ,  Ali Shafiee Ardestani ,  Joseph H. Hassoun ,  Lei Wang ,  Sehwan Lee ,  JoonHo Song ,  Jun-Woo Jang ,  Yibing Michelle Wang ,  Yuecheng Li

IPC: G06N3/04 ,  G06F9/30 ,  G06F17/15 ,  G06F17/16 ,  G06N3/08 ,  G06T9/00

CPC classification number: G06N3/04 ,  G06F17/153 ,  G06F17/16 ,  G06N3/08 ,  G06T9/002 ,  G06F9/3001

Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.

公开(公告)号：US11954574B2

公开(公告)日：2024-04-09

申请号：US16446610

申请日：2019-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilia Ovsiannikov ,  Ali Shafiee Ardestani ,  Joseph H. Hassoun ,  Lei Wang ,  Sehwan Lee ,  JoonHo Song ,  Jun-Woo Jang ,  Yibing Michelle Wang ,  Yuecheng Li

IPC: G06N3/04 ,  G06F9/30 ,  G06F17/15 ,  G06F17/16 ,  G06N3/08 ,  G06T9/00

CPC classification number: G06N3/04 ,  G06F17/153 ,  G06F17/16 ,  G06N3/08 ,  G06T9/002 ,  G06F9/3001

Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.

公开(公告)号：US20200026978A1

公开(公告)日：2020-01-23

申请号：US16552619

申请日：2019-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilia Ovsiannikov ,  Ali Shafiee Ardestani ,  Joseph H. Hassoun ,  Lei Wang ,  Sehwan Lee ,  JoonHo Song ,  Jun-Woo Jang ,  Yibing Michelle Wang ,  Yuecheng Li

IPC: G06N3/04 ,  G06F17/16 ,  G06N3/08

Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.

公开(公告)号：US11783161B2

公开(公告)日：2023-10-10

申请号：US16446610

申请日：2019-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilia Ovsiannikov ,  Ali Shafiee Ardestani ,  Joseph H. Hassoun ,  Lei Wang ,  Sehwan Lee ,  JoonHo Song ,  Jun-Woo Jang ,  Yibing Michelle Wang ,  Yuecheng Li

IPC: G06N3/04 ,  G06F17/16 ,  G06F9/30 ,  G06N3/08 ,  G06F17/15 ,  G06T9/00

CPC classification number: G06N3/04 ,  G06F17/153 ,  G06F17/16 ,  G06N3/08 ,  G06T9/002 ,  G06F9/3001

Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.

公开(公告)号：US11775802B2

公开(公告)日：2023-10-03

申请号：US16552945

申请日：2019-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilia Ovsiannikov ,  Ali Shafiee Ardestani ,  Joseph H. Hassoun ,  Lei Wang ,  Sehwan Lee ,  JoonHo Song ,  Jun-Woo Jang ,  Yibing Michelle Wang ,  Yuecheng Li

IPC: G06N3/04 ,  G06F17/16 ,  G06F17/15 ,  G06N3/08 ,  G06T9/00 ,  G06F9/30

CPC classification number: G06N3/04 ,  G06F17/153 ,  G06F17/16 ,  G06N3/08 ,  G06T9/002 ,  G06F9/3001

Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.

公开(公告)号：US11775801B2

公开(公告)日：2023-10-03

申请号：US16552850

申请日：2019-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilia Ovsiannikov ,  Ali Shafiee Ardestani ,  Joseph H. Hassoun ,  Lei Wang ,  Sehwan Lee ,  JoonHo Song ,  Jun-Woo Jang ,  Yibing Michelle Wang ,  Yuecheng Li

IPC: G06N3/04 ,  G06F17/16 ,  G06F9/30 ,  G06N3/08 ,  G06F17/15 ,  G06T9/00

CPC classification number: G06N3/04 ,  G06F17/153 ,  G06F17/16 ,  G06N3/08 ,  G06T9/002 ,  G06F9/3001

Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.

公开(公告)号：US20200026980A1

公开(公告)日：2020-01-23

申请号：US16552945

申请日：2019-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilia Ovsiannikov ,  Ali Shafiee Ardestani ,  Joseph H. Hassoun ,  Lei Wang ,  Sehwan Lee ,  JoonHo Song ,  Jun-Woo Jang ,  Yibing Michelle Wang ,  Yuecheng Li

IPC: G06N3/04 ,  G06F17/16 ,  G06N3/08

Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.

公开(公告)号：US20190392287A1

公开(公告)日：2019-12-26

申请号：US16446610

申请日：2019-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilia Ovsiannikov ,  Ali Shafiee Ardestani ,  Joseph H. Hassoun ,  Lei Wang ,  Sehwan Lee ,  JoonHo Song ,  Jun-Woo Jang ,  Yibing Michelle Wang ,  Yuecheng Li

IPC: G06N3/04 ,  G06N3/08 ,  G06F17/16

Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.

公开(公告)号：US12255721B2

公开(公告)日：2025-03-18

申请号：US18313568

申请日：2023-05-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Liying Zhou ,  Lei Wang ,  Yiyan Zhang ,  He Wang ,  Songhui Shen ,  Chaeman Lim

IPC: H04B7/06 ,  H04L5/00

Abstract: A method which may be performed by a base station, may include obtaining a predicted transmission configuration indicator (TCI) subset for a user equipment (UE); and determining the TCI subset corresponding to the UE based on the predicted TCI subset. The step of obtaining the predicted TCI subset in the solution may be implemented by using a trained artificial intelligence model. Since the beams in the predicted TCI subset may fit the movement trend of the UE, then the target serving beam for the UE when performing serving beam switching may belong to the predicted TCI subset with a greater possibility, thus reducing the occurrence of high delay scenarios when the UE performs the serving beam switching, and thus reducing the beam switching delay.

公开(公告)号：US12099912B2

公开(公告)日：2024-09-24

申请号：US16446610

申请日：2019-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilia Ovsiannikov ,  Ali Shafiee Ardestani ,  Joseph H. Hassoun ,  Lei Wang ,  Sehwan Lee ,  JoonHo Song ,  Jun-Woo Jang ,  Yibing Michelle Wang ,  Yuecheng Li

IPC: G06N3/04 ,  G06F9/30 ,  G06F17/15 ,  G06F17/16 ,  G06N3/08 ,  G06T9/00

CPC classification number: G06N3/04 ,  G06F17/153 ,  G06F17/16 ,  G06N3/08 ,  G06T9/002 ,  G06F9/3001

Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.