公开(公告)号：US10777579B2

公开(公告)日：2020-09-15

申请号：US16543220

申请日：2019-08-16

Applicant: SOCIONEXT INC.

Inventor： Junji Iwahori

IPC: H01L27/118 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786

Abstract: In a semiconductor integrated circuit device using three-dimensional transistor devices, a delay cell having a large delay value per unit area is implemented. A first cell, which is a logic cell, includes three-dimensional transistor devices. A second cell, which is a delay cell, includes three-dimensional transistor devices. The length by which a second local interconnect protrudes from a second solid diffusion layer portion in a direction away from a power supply interconnect in the second cell is greater than the length by which a first local interconnect protrudes from a first solid diffusion layer portion in a direction away from the power supply interconnect in the first cell.