公开(公告)号：US09425771B2

公开(公告)日：2016-08-23

申请号：US14498048

申请日：2014-09-26

Applicant: Texas Instruments Incorporated

Inventor： Suvam Nandi ,  Badarish Mohan Subbannavar

IPC: H03K3/356 ,  H03K3/012 ,  H03K3/3562

CPC classification number: H03K3/012 ,  H03K3/35606 ,  H03K3/35625

Abstract: A flip-flop is disclosed that utilizes low area. The flip-flop includes a tri-state inverter that receive a flip-flop input, a clock input and an inverted clock input. A master latch receives an output of the tri-state inverter. The master latch includes a common inverter. A slave latch is coupled to the master latch. The common inverter is shared between the master latch and the slave latch. An output inverter is coupled to the common inverter and generates a flip-flop output.

Abstract translation: 公开了一种使用低面积的触发器。 触发器包括三态反相器，其接收触发器输入，时钟输入和反相时钟输入。 主锁存器接收三态反相器的输出。 主锁存器包括一个公共的逆变器。 从锁存器耦合到主锁存器。 公共逆变器在主锁存器和从锁存器之间共享。 输出反相器耦合到公共反相器并产生触发器输出。

公开(公告)号：US20160094203A1

公开(公告)日：2016-03-31

申请号：US14498048

申请日：2014-09-26

Applicant: Texas Instruments Incorporated

Inventor： Suvam Nandi ,  Badarish Mohan Subbannavar

IPC: H03K3/012 ,  H03K3/3562

CPC classification number: H03K3/012 ,  H03K3/35606 ,  H03K3/35625

Abstract: A flip-flop is disclosed that utilizes low area. The flip-flop includes a tri-state inverter that receive a flip-flop input, a clock input and an inverted clock input. A master latch receives an output of the tri-state inverter. The master latch includes a common inverter. A slave latch is coupled to the master latch. The common inverter is shared between the master latch and the slave latch. An output inverter is coupled to the common inverter and generates a flip-flop output.

Abstract translation: 公开了一种使用低面积的触发器。 触发器包括三态反相器，其接收触发器输入，时钟输入和反相时钟输入。 主锁存器接收三态反相器的输出。 主锁存器包括一个公共的逆变器。 从锁存器耦合到主锁存器。 公共逆变器在主锁存器和从锁存器之间共享。 输出反相器耦合到公共反相器并产生触发器输出。

公开(公告)号：US20160092170A1

公开(公告)日：2016-03-31

申请号：US14496767

申请日：2014-09-25

Applicant: Texas Instruments Incorporated

Inventor： Suvam Nandi ,  Badarish Mohan Subbannavar

IPC: G06F7/50 ,  H03K19/00 ,  H03K19/20

CPC classification number: G06F7/50 ,  G06F7/501 ,  H03K19/0013 ,  H03K19/20

Abstract: A full adder is disclosed that utilizes low area. The full adder includes an exclusive NOR logic circuit. The exclusive NOR logic circuit receives a first input and a second input. A first inverter receives an output of the exclusive NOR logic circuit and generates an exclusive OR output. A carry generation circuit receives the output of the exclusive NOR logic circuit, the exclusive OR output and a third input. The carry generation circuit generates an inverted carry. A second inverter is coupled to the carry generation circuit and generates a carry on receiving the inverted carry. A sum generation circuit receives the output of the exclusive NOR logic circuit, the exclusive OR output and the third input. The sum generation circuit generates an inverted sum. A third inverter is coupled to the sum generation circuit and generates a sum on receiving the inverted sum.

Abstract translation: 公开了一种利用低面积的全加器。 全加器包括一个异或逻辑电路。 异或逻辑电路接收第一输入和第二输入。 第一反相器接收异或逻辑电路的输出并产生异或输出。 进位发生电路接收异或逻辑电路的输出，异或输出和第三输入。 进位发生电路产生反转进位。 第二反相器耦合到进位发生电路，并产生接收反向进位的进位。 和产生电路接收异或逻辑电路的输出，异或输出和第三输入。 和产生电路产生一个反相和。 第三反相器耦合到和产生电路，并在接收到反相和时产生和。