Abstract:
A display panel and a display apparatus are provided. The display panel includes: a first edge and a second edge configured along a first direction and facing opposite to each other; a third edge and a fourth edge configured along a second direction and facing opposite to each other; a display area; and a non-display area surrounding the display area and including a binding area disposed adjacent to the first edge. The binding area includes a first sub-area adjacent to the third edge and a second sub-area adjacent to the fourth edge. Each of the first and second sub-areas includes a plurality of binding soldering pads arranged along the second direction. Each of the plurality of binding soldering pads includes a first section, a second section, and a third section.
Abstract:
Display panel and display device are provided. An exemplary display panel includes a display area and a non-display area surrounding the display area. The display area includes a plurality of gate lines, a plurality of data lines, and an irregularly-shaped edge. The non-display area includes a first non-display area adjacent to the irregularly-shaped edge. The first non-display area includes a first sub-area adjacent to the sub-edge. The plurality of data lines includes a plurality of irregularly-shaped data lines. The plurality of irregularly-shaped data lines includes a plurality of winding portions in the first sub-area which includes at least one first winding portion, and the at least one first winding portion has at least a wiring portion in a film layer different than a remaining portion of the plurality of winding portions.
Abstract:
A display panel and a display device are provided. The display panel includes multiple pixel units. In each of the pixel units, the area of an opening region of at least one sub-pixel is different from the area of an opening region of other sub-pixels. There is an adjustment capacitance between the drain of the thin film transistor and/or the first electrode in each sub-pixel and the scan line corresponding to the sub-pixel, and the sub-pixel having a smaller area of the opening region corresponds to a smaller value of the adjustment capacitance. By adjusting the value of the adjustment capacitance corresponding to the sub-pixels with different areas of opening regions, the optimal Vcom of all the sub-pixels is the same, so that all the sub-pixels operate under the same optimal Vcom.
Abstract:
The present disclosure provides a display panel and display device. Display panel includes: a plurality of first sub-pixel groups and a plurality of second sub-pixel groups, the first sub-pixel group each including a plurality of first sub-pixels, the second sub-pixel groups each including a plurality of second sub-pixels, a contribution value of the first sub-pixels to the illumination brightness of the display panel being greater than that of the second sub-pixels to the illumination brightness of the display panel; a first data line connected to the first sub-pixels in the first sub-pixel group; a second data line connected to the second sub-pixels in the second sub-pixel group; a plurality of touch electrodes and a plurality of touch signal lines, a distance from the touch signal line to its closest second data line being smaller than a distance from the touch signal line to its closest first data line.
Abstract:
Provided are a display panel, a driving method thereof and a display device, for improving the quality of displayed images and reducing the power consumption. The display panel includes first and second pixel units of opposite polarities, and first and second data lines for transmitting signals of opposite polarities. The first and the second pixel units each includes at least two sub-pixels of different colors. The first data line is connected to the first pixel units in the (j−1)th and jth columns of sub-pixels. Sub-pixels in the first pixel unit in the (j−1)th column have different colors from those in the first pixel unit in the jth column. The second data line is connected to the second pixel units in the jth and (j+1)th columns. Sub-pixels in the second pixel unit in the jth column have different colors from those in the second pixel unit in the (j+1)th column.
Abstract:
A touch control display panel and a display device are provided. The touch control display panel may comprise a plurality of touch driving electrodes arranged in a first direction; a touch sensing electrode array including a plurality of touch sensing electrode rows arranged in a second direction, wherein a touch sensing electrode row includes a first touch sensing electrode and a second touch sensing electrode arranged in the first direction. In a same touch sensing electrode row, a gap is provided between the first touch sensing electrode and the second touch sensing electrode, and the gap has a width of w1 in the first direction, the touch driving electrode disposed opposite to and over the gap between the first touch sensing electrode and the second touch sensing electrode has an electrode width of w2 in the first direction, and the gap width w1 is smaller than the electrode width w2.
Abstract:
A color filter plate, a color filter plate fabrication method and a display panel are provided. The color filter plate comprises a substrate and a plurality of color filter elements alternately arranged on the substrate. Each color filter element includes two edge portions and one body portion between the two edge portions. The plurality of color filter elements further comprises a plurality of first color filter elements, and at least one edge portion of each first color filter element is thicker than the body portion of each first color filter element.
Abstract:
An array substrate, and a display panel and display device including the same are disclosed. An embodiment of the array substrate comprises a display region and a non-display region. The non-display region comprises: abase substrate; and a first metal layer, a second metal layer, and a third metal layer arranged in a direction perpendicular to the base substrate. A transistor and a metal line are arranged in the non-display region. A gate electrode of the transistor is located in the first metal layer. A source electrode and a drain electrode of the transistor are located in the second metal layer. The metal line is located in the third metal layer. The orthographic projection of the transistor onto the base substrate overlaps, at least partially, with the orthographic projection of the metal line onto the base substrate.
Abstract:
A touch array substrate includes a substrate and a touch sensing electrode layer including a plurality of touch sensing electrodes; a touch sensing electrode line layer includes a plurality of touch sensing electrode lines and a plurality of virtual touch sensing electrode lines; each of the touch sensing electrodes is electrically connected with at least one of the touch sensing electrode lines; at least one of the touch sensing electrodes includes a first slot and a second slot; a third region which represents a projection of the second slot on the substrate is separated from a projection of each of the touch sensing electrode lines, and the third region is at least partially overlapped with a projection of the respective one of the virtual touch sensing electrode lines on the substrate.
Abstract:
The present invention discloses a TFT array substrate and a manufacturing method thereof and a liquid crystal display device, which is aiming at lowering the resistance value of a common electrode and not diminishing the aperture ratio of pixels on the premise that the manufacturing cost is not additionally increased. The TFT array substrate includes: a substrate, a common electrode layer arranged on the substrate, a first insulating layer arranged on the common electrode layer and a plurality of pixel electrodes arranged in an array on the first insulating layer, wherein via holes penetrating through the first insulating layer are formed between adjacent pixels in some of a plurality of pixels, and common electrode lines are grown between rows and/or columns of pixels in some of the plurality of pixels, and in parallel with the common electrode layer below the first insulating layer through the via holes.