公开(公告)号：US07600207B2

公开(公告)日：2009-10-06

申请号：US11363889

申请日：2006-02-27

申请人： Victor Moroz ,  Dipankar Pramanik ,  Xi-Wei Lin

发明人： Victor Moroz ,  Dipankar Pramanik ,  Xi-Wei Lin

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  H01L21/823807

摘要： Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors.

摘要翻译： 大致描述了改进集成电路布局和制造工艺的方法和系统，以便更好地解决应力影响。 为了改善均匀性或放松已知的不良应力或引入已知的所需应力，可将虚拟特征添加到布局中。 虚拟特征可以包括添加以放松应力的虚拟扩散区域，并且添加虚拟沟槽以放松或增强应力。 沟槽可以通过用应力中性材料或拉伸应变材料填充来缓解应力。 沟槽可以通过用压缩应变材料填充来增加应力。 优选地，虚拟扩散区域和应力松弛沟槽纵向设置在N沟道晶体管的至少沟道区域上，并横向于N沟道和P沟道晶体管的至少沟道区域。 优选地，应力增强沟槽纵向设置在至少P沟道晶体管的沟道区域上。

公开(公告)号：US07484198B2

公开(公告)日：2009-01-27

申请号：US11364390

申请日：2006-02-27

申请人： Xi-Wei Lin ,  Dipankar Pramanik ,  Victor Moroz

发明人： Xi-Wei Lin ,  Dipankar Pramanik ,  Victor Moroz

IPC分类号： G06F17/50

CPC分类号： H01L21/823878 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7846

摘要： Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors.

摘要翻译： 大致描述了改进集成电路布局和制造工艺的方法和系统，以便更好地解决应力影响。 为了改善均匀性或放松已知的不良应力或引入已知的所需应力，可将虚拟特征添加到布局中。 虚拟特征可以包括添加以放松应力的虚拟扩散区域，并且添加虚拟沟槽以放松或增强应力。 沟槽可以通过用应力中性材料或拉伸应变材料填充来缓解应力。 沟槽可以通过用压缩应变材料填充来增加应力。 优选地，虚拟扩散区域和应力松弛沟槽纵向设置在N沟道晶体管的至少沟道区域上，并横向于N沟道和P沟道晶体管的至少沟道区域。 优选地，应力增强沟槽纵向设置在至少P沟道晶体管的沟道区域上。

公开(公告)号：US20070204250A1

公开(公告)日：2007-08-30

申请号：US11363889

申请日：2006-02-27

申请人： Victor Moroz ,  Dipankar Pramanik ,  Xi-Wei Lin

发明人： Victor Moroz ,  Dipankar Pramanik ,  Xi-Wei Lin

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  H01L21/823807

摘要： Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors.

摘要翻译： 大致描述了改进集成电路布局和制造工艺的方法和系统，以便更好地解决应力影响。 为了改善均匀性或放松已知的不良应力或引入已知的所需应力，可将虚拟特征添加到布局中。 虚拟特征可以包括添加以放松应力的虚拟扩散区域，并且添加虚拟沟槽以放松或增强应力。 沟槽可以通过用应力中性材料或拉伸应变材料填充来缓解应力。 沟槽可以通过用压缩应变材料填充来增加应力。 优选地，虚拟扩散区域和应力松弛沟槽纵向设置在N沟道晶体管的至少沟道区域上，并横向于N沟道和P沟道晶体管的至少沟道区域。 优选地，应力增强沟槽纵向设置在至少P沟道晶体管的沟道区域上。

公开(公告)号：US20070202663A1

公开(公告)日：2007-08-30

申请号：US11364392

申请日：2006-02-27

申请人： Victor Moroz ,  Dipankar Pramanik ,  Xi-Wei Lin

发明人： Victor Moroz ,  Dipankar Pramanik ,  Xi-Wei Lin

IPC分类号： H01L21/76

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/7846 ,  H01L29/7848

摘要： Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors.

摘要翻译： 大致描述了改进集成电路布局和制造工艺的方法和系统，以便更好地解决应力影响。 为了改善均匀性或放松已知的不良应力或引入已知的所需应力，可将虚拟特征添加到布局中。 虚拟特征可以包括添加以放松应力的虚拟扩散区域，并且添加虚拟沟槽以放松或增强应力。 沟槽可以通过用应力中性材料或拉伸应变材料填充来缓解应力。 沟槽可以通过用压缩应变材料填充来增加应力。 优选地，虚拟扩散区域和应力松弛沟槽纵向设置在N沟道晶体管的至少沟道区域上，并横向于N沟道和P沟道晶体管的至少沟道区域。 优选地，应力增强沟槽纵向设置在至少P沟道晶体管的沟道区域上。

公开(公告)号：US07895548B2

公开(公告)日：2011-02-22

申请号：US11924738

申请日：2007-10-26

申请人： Xi Wei Lin ,  Jyh-Chwen Frank Lee ,  Dipankar Pramanik

发明人： Xi Wei Lin ,  Jyh-Chwen Frank Lee ,  Dipankar Pramanik

IPC分类号： G06F17/50

CPC分类号： G06F17/50 ,  G06F17/5068 ,  H01L27/0207

摘要： A system and method are provided for laying out an integrated circuit design into a plurality of circuit layout cells having gaps therebetween, and inserting into each given one of at least a subset of the gaps, a corresponding filler cell selected from a predefined database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap. The circuit layout cells may be arranged in rows, and in some embodiments the selection of an appropriate filler cell for a given gap depends upon effects desired on a performance parameter of both circuit cells adjacent to the given gap. The predefined filler cells can include, for example, dummy diffusion regions, dummy poly lines, N-well boundary shifts and etch stop layer boundary shifts. In an embodiment, circuit layout cells can be moved in order to accommodate a selected filler cell.

摘要翻译： 提供了一种系统和方法，用于将集成电路设计布置成具有间隙的多个电路布局单元，并且将至少一个子空间中的每个给定的一个插入到依赖于预定数据库的相应填充单元 对所述给定间隙相邻的至少一个电路单元的性能参数产生期望的影响。 电路布局单元可以排成行，并且在一些实施例中，用于给定间隙的适当填充单元的选择取决于与给定间隙相邻的两个电路单元的性能参数所期望的效果。 预定义的填充单元可以包括例如虚拟扩散区域，虚拟多线，N阱边界位移和蚀刻停止层边界移位。 在一个实施例中，可以移动电路布局单元以便容纳选定的填充单元。

公开(公告)号：US07739095B2

公开(公告)日：2010-06-15

申请号：US11685250

申请日：2007-03-13

申请人： Xi-Wei Lin ,  Dipankar Pramanik

发明人： Xi-Wei Lin ,  Dipankar Pramanik

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： Roughly described, signal propagation delay values are estimated for a plurality of interconnects in a circuit design. For each interconnect, the propagation delay value(s) are estimated in dependence upon a preliminary approximate determination of whether the signal propagation delay is dominated more by an interconnect capacitance term or by an interconnect capacitance and resistance product term. If it is dominated more by the interconnect capacitance term, then the parameter values used for a minimum propagation delay calculation are obtained assuming a smallest capacitance process variation case and the parameter values used for a maximum propagation delay calculation are obtained assuming a largest capacitance process variation case. If the signal propagation delay is dominated more by the interconnect capacitance and resistance product term, then the opposite assumptions are made. Preferably the approximate determination is made by comparing Rint to k*Rd.

摘要翻译： 粗略描述，在电路设计中为多个互连估计信号传播延迟值。 对于每个互连，传播延迟值根据初步近似确定信号传播延迟是否由互连电容项或互连电容和电阻乘积项更多地支配来估计。 如果更多地被互连电容项支配，则假定最小传播延迟计算使用的参数值是假定最小电容处理变化情况，并且假定最大电容处理变化获得用于最大传播延迟计算的参数值 案件。 如果信号传播延迟更多地被互连电容和电阻乘积项所主导，则进行相反的假设。 优选地，通过将​​Rint与k * Rd进行比较来进行近似确定。

公开(公告)号：US20090113368A1

公开(公告)日：2009-04-30

申请号：US11924738

申请日：2007-10-26

申请人： Xi-Wei Lin ,  Jyh-Chwen Frank Lee ,  Dipankar Pramanik

发明人： Xi-Wei Lin ,  Jyh-Chwen Frank Lee ,  Dipankar Pramanik

IPC分类号： G06F17/50

CPC分类号： G06F17/50 ,  G06F17/5068 ,  H01L27/0207

摘要： A system and method are provided for laying out an integrated circuit design into a plurality of circuit layout cells having gaps therebetween, and inserting into each given one of at least a subset of the gaps, a corresponding filler cell selected from a predefined database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap. The circuit layout cells may be arranged in rows, and in some embodiments the selection of an appropriate filler cell for a given gap depends upon effects desired on a performance parameter of both circuit cells adjacent to the given gap. The predefined filler cells can include, for example, dummy diffusion regions, dummy poly lines, N-well boundary shifts and etch stop layer boundary shifts. In an embodiment, circuit layout cells can be moved in order to accommodate a selected filler cell.

摘要翻译： 提供了一种系统和方法，用于将集成电路设计布置成具有间隙的多个电路布局单元，并且将至少一个子空间中的每个给定的一个插入到依赖于预定数据库的相应填充单元 对所述给定间隙相邻的至少一个电路单元的性能参数产生期望的影响。 电路布局单元可以排成行，并且在一些实施例中，用于给定间隙的适当填充单元的选择取决于与给定间隙相邻的两个电路单元的性能参数所期望的效果。 预定义的填充单元可以包括例如虚拟扩散区域，虚拟多线，N阱边界位移和蚀刻停止层边界移位。 在一个实施例中，可以移动电路布局单元以便容纳选定的填充单元。

公开(公告)号：US06316834B1

公开(公告)日：2001-11-13

申请号：US09392343

申请日：1999-09-08

申请人： Calvin T. Gabriel ,  Dipankar Pramanik ,  Xi-Wei Lin

发明人： Calvin T. Gabriel ,  Dipankar Pramanik ,  Xi-Wei Lin

IPC分类号： H01L2348

CPC分类号： H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for producing a glue layer for an integrated circuit which uses tungsten plugs in accordance with the present invention includes: (A) providing a substrate which has a surface, a center, an edge, and a direction normal to the surface; and (B) sputter depositing a glue layer over the surface of the substrate such that an edge thickness of the glue layer measured in the direction normal to the surface at the edge of the substrate is at least 105% of a center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate. In some embodiments, the edge thickness of said glue layer measured in the direction normal to the surface at the edge of the substrate is in the range of approximately 105% to 150% of the center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate, as for example in the range of approximately 110% to 120% of the center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate.

摘要翻译： 根据本发明的使用钨丝塞的集成电路胶层的制造方法包括：（A）提供具有表面，中心，边缘和与该表面垂直的方向的基板; 和（B）在衬底的表面上溅射沉积胶层，使得在垂直于衬底边缘表面的方向上测量的胶层的边缘厚度为胶的中心厚度的至少105％ 层在垂直于衬底中心表面的方向上测量。 在一些实施例中，在垂直于衬底边缘处的表面的方向上测量的所述胶层的边缘厚度在胶层的中心厚度的约105％至150％的范围内，其测量方向为垂直于 在基板的中心处的表面，例如在垂直于基板中心的表面的方向上测量的胶层的中心厚度的约110％至120％的范围内。

公开(公告)号：US5834356A

公开(公告)日：1998-11-10

申请号：US883814

申请日：1997-06-27

申请人： Subhas Bothra ,  Dipankar Pramanik ,  Xi-Wei Lin

发明人： Subhas Bothra ,  Dipankar Pramanik ,  Xi-Wei Lin

IPC分类号： H01L21/02 ,  H01L21/285 ,  H01L21/20

CPC分类号： H01L28/24 ,  H01L21/28518 ,  H01L28/20

摘要： Disclosed is a method for making a high resistive structure in a salicided process. The method includes providing a substrate including at least one active device having diffusion regions and a polysilicon gate structure. Depositing a metallization layer over the substrate including at least one active device. Annealing the substrate to cause at least part of metallization layer to form a metallization silicided layer over the substrate that includes the at least one active device. Preferably, the metallization silicided layer lying over the diffusion regions and the polysilicon gate produces a substantially decreased level of sheet resistance. The method also includes forming a mask over the metallization silicided layer, and the mask being configured to leave a portion of the metallization silicided layer that overlies at least one active device exposed. Further, the method includes etching the substrate in order to remove the exposed metallization silicided layer overlying the at least one active device to produce a substantially increased level of sheet resistance over the at least one active device not having the metallization silicided layer.

摘要翻译： 本发明公开了一种在水银工艺中制作高电阻结构的方法。 该方法包括提供包括至少一个具有扩散区的有源器件和多晶硅栅极结构的衬底。 在包括至少一个有源器件的衬底上沉积金属化层。 退火衬底以使至少部分金属化层在包括至少一个有源器件的衬底上形成金属化硅化物层。 优选地，位于扩散区域和多晶硅栅极上方的金属化硅化物层产生显着降低的薄层电阻水平。 该方法还包括在金属化硅化物层上形成掩模，并且掩模被配置为留下覆盖至少一个暴露的有源器件的金属化硅化物层的一部分。 此外，该方法包括蚀刻衬底以去除覆盖至少一个有源器件的暴露的金属化硅化物层，以在不具有金属化硅化物层的至少一个有源器件上产生基本上增加的片电阻水平。

公开(公告)号：US08504969B2

公开(公告)日：2013-08-06

申请号：US12961732

申请日：2010-12-07

申请人： Xi-Wei Lin ,  Jyh-Chwen Frank Lee ,  Dipankar Pramanik

发明人： Xi-Wei Lin ,  Jyh-Chwen Frank Lee ,  Dipankar Pramanik

IPC分类号： G06F17/50

CPC分类号： G06F17/50 ,  G06F17/5068 ,  H01L27/0207

摘要： A system and method are provided for laying out an integrated circuit design into a plurality of circuit layout cells having gaps therebetween, and inserting into each given one of at least a subset of the gaps, a corresponding filler cell selected from a predefined database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap. The circuit layout cells may be arranged in rows, and in some embodiments the selection of an appropriate filler cell for a given gap depends upon effects desired on a performance parameter of both circuit cells adjacent to the given gap. The predefined filler cells can include, for example, dummy diffusion regions, dummy poly lines, N-well boundary shifts and etch stop layer boundary shifts. In an embodiment, circuit layout cells can be moved in order to accommodate a selected filler cell.

摘要翻译： 提供了一种系统和方法，用于将集成电路设计布置成具有间隙的多个电路布局单元，并且将至少一个子空间中的每个给定的一个插入到依赖于预定数据库的相应填充单元 对所述给定间隙相邻的至少一个电路单元的性能参数产生期望的影响。 电路布局单元可以排成行，并且在一些实施例中，用于给定间隙的适当填充单元的选择取决于与给定间隙相邻的两个电路单元的性能参数所期望的效果。 预定义的填充单元可以包括例如虚拟扩散区域，虚拟多线，N阱边界位移和蚀刻停止层边界移位。 在一个实施例中，可以移动电路布局单元以便容纳选定的填充单元。