摘要:
An integrated circuit (IC) includes a first processing module that converts inbound data into an inbound digital audio signal and converts an outbound digital audio signal into outbound data. A second processing module performs a user application that includes at least one of generating of an inbound analog audio signal and generating an outbound analog audio signal. A third processing module performs an operating system algorithm to coordinate operation of at least one user application.
摘要:
An integrated circuit (IC) includes an RF section, a DSP, and a plurality of processors. The RF section and the DSP process an inbound RF signal to produce inbound data and process outbound data to produce an outbound RF signal. In addition, the DSP converts an outbound analog audio signal into an outbound digital audio signal and converts an inbound digital audio signal into an inbound analog audio signal. A first processor converts the inbound data into the inbound digital audio signal and converts the outbound digital audio signal into the outbound data. A second processor performs a user application that includes at least one of generation of the inbound analog audio signal and generation of the outbound analog audio signal and performs an operating system algorithm to coordinate operation of the user application.
摘要:
An integrated circuit (IC) includes at least one baseband section, at least one radio frequency (RF) section, and an interface module. The interface module is configured to couple the at least one baseband section to the at least one RF section, wherein the interface module includes an analog interface module and a digital interface module.
摘要:
An integrated circuit (IC) includes an RF section, a DSP, and a plurality of processors. The RF section and the DSP process an inbound RF signal to produce inbound data and process outbound data to produce an outbound RF signal. In addition, the DSP converts an outbound analog audio signal into an outbound digital audio signal and converts an inbound digital audio signal into an inbound analog audio signal. A first processor converts the inbound data into the inbound digital audio signal and converts the outbound digital audio signal into the outbound data. A second processor performs a user application that includes at least one of generation of the inbound analog audio signal and generation of the outbound analog audio signal and performs an operating system algorithm to coordinate operation of the user application.
摘要:
An integrated circuit (IC) includes at least one baseband section, at least one radio frequency (RF) section, and an interface module. The interface module is operable to couple the at least one baseband section to the at least one RF section, wherein the interface module includes an analog interface module and a digital interface module.
摘要:
A single chip wireless transceiver operable to perform voice, data and radio frequency (RF) processing is provided. This processing may be divided between various processing modules. This single chip includes a processing module having an ARM microprocessor and a digital signal processor (DSP), an RF section, and an interface module. The processing module converts an outbound voice signal into an outbound voice symbol stream, converts an inbound voice symbol stream into an inbound voice signal, converts outbound data into an outbound data symbol stream, and converts an inbound data symbol stream into inbound data. These functions may be divided between the ARM microprocessor and DSP, where the DSP supports physically layer type applications and the ARM microprocessor supports higher layer applications. Further bifurcation may be based on voice applications, data applications, and/or RF control. The RF section converts an inbound RF voice signal into the inbound voice symbol stream, converts the outbound voice symbol stream into an outbound RF voice signal, converts an inbound RF data signal into the inbound data symbol stream, and converts the outbound data symbol stream into an outbound RF data signal. The interface module provides coupling between the processing module, the RF section, and with off-chip circuits.
摘要:
A single chip wireless transceiver operable to perform voice, data and radio frequency (RF) processing is provided. This processing may be divided between various processing modules. This single chip includes a processing module having an ARM microprocessor and a digital signal processor (DSP), an RF section, and an interface module. The processing module converts an outbound voice signal into an outbound voice symbol stream, converts an inbound voice symbol stream into an inbound voice signal, converts outbound data into an outbound data symbol stream, and converts an inbound data symbol stream into inbound data. These functions may be divided between the ARM microprocessor and DSP, where the DSP supports physically layer type applications and the ARM microprocessor supports higher layer applications. Further bifurcation may be based on voice applications, data applications, and/or RF control. The RF section converts an inbound RF voice signal into the inbound voice symbol stream, converts the outbound voice symbol stream into an outbound RF voice signal, converts an inbound RF data signal into the inbound data symbol stream, and converts the outbound data symbol stream into an outbound RF data signal. The interface module provides coupling between the processing module, the RF section, and with off-chip circuits.
摘要:
A single chip wireless transceiver operable to perform voice, data and radio frequency (RF) processing is provided. This processing may be divided between various processing modules. This single chip includes a processing module having an ARM microprocessor and a digital signal processor (DSP), an RF section, and an interface module. The processing module converts an outbound voice signal into an outbound voice symbol stream, converts an inbound voice symbol stream into an inbound voice signal, converts outbound data into an outbound data symbol stream, and converts an inbound data symbol stream into inbound data. These functions may be divided between the ARM microprocessor and DSP, where the DSP supports physically layer type applications and the ARM microprocessor supports higher layer applications. Further bifurcation may be based on voice applications, data applications, and/or RF control. The RF section converts an inbound RF voice signal into the inbound voice symbol stream, converts the outbound voice symbol stream into an outbound RF voice signal, converts an inbound RF data signal into the inbound data symbol stream, and converts the outbound data symbol stream into an outbound RF data signal. The interface module provides coupling between the processing module, the RF section, and with off-chip circuits.
摘要:
A single chip wireless transceiver operable to perform voice, data and radio frequency (RF) processing is provided. This processing may be divided between various processing modules. This single chip includes a processing module having an ARM microprocessor and a digital signal processor (DSP), an RF section, and an interface module. The processing module converts an outbound voice signal into an outbound voice symbol stream, converts an inbound voice symbol stream into an inbound voice signal, converts outbound data into an outbound data symbol stream, and converts an inbound data symbol stream into inbound data. These functions may be divided between the ARM microprocessor and DSP, where the DSP supports physically layer type applications and the ARM microprocessor supports higher layer applications. Further bifurcation may be based on voice applications, data applications, and/or RF control. The RF section converts an inbound RF voice signal into the inbound voice symbol stream, converts the outbound voice symbol stream into an outbound RF voice signal, converts an inbound RF data signal into the inbound data symbol stream, and converts the outbound data symbol stream into an outbound RF data signal. The interface module provides coupling between the processing module, the RF section, and with off-chip circuits.
摘要:
An RFIC includes first and second RF sections, first and second PHY processing modules, first and second upper layer processing modules, and memory. When the RFIC is in a first receive mode, the first RF section, the first PHY processing module, and the first upper layers processing module convert a first inbound RF signal into a first inbound audio signal in accordance with a first wireless communication protocol. When the RFIC is in a second receive mode, the second RF section, the second PHY processing module, and the second upper layers processing module convert a second inbound RF signal into a second inbound audio signal in accordance with a second wireless communication protocol. The memory stores the first and second inbound audio signals. The first PHY processing module retrieves, based on the receive mode, the first or second inbound audio signal from the memory and converts the first or second inbound audio signal into a first or second inbound analog audio signal.