Diagnostic test pattern generation for small delay defect
    21.
    发明授权
    Diagnostic test pattern generation for small delay defect 有权
    诊断测试模式生成小延迟缺陷

    公开(公告)号:US08527232B2

    公开(公告)日:2013-09-03

    申请号:US12768592

    申请日:2010-04-27

    IPC分类号: G01R31/00

    CPC分类号: G01R31/318328

    摘要: Methods of diagnostic test pattern generation for small delay defects are based on identification and activation of long paths passing through diagnosis suspects. The long paths are determined according to some criteria such as path delay values calculated with SDF (Standard Delay Format) timing information and the number of logic gates on a path. In some embodiments of the invention, the long paths are the longest paths passing through a diagnosis suspect and reaching a corresponding failing observation point selected from the failure log, and N longest paths are identified for each of such pairs.

    摘要翻译: 小延迟缺陷的诊断测试模式生成方法基于识别和激活穿过诊断嫌疑人的长途径。 根据某些标准确定长路径,例如使用SDF(标准延迟格式)定时信息计算的路径延迟值和路径上的逻辑门数。 在本发明的一些实施例中,长路径是穿过诊断嫌疑人并且到达从故障日志中选择的相应故障观察点的最长路径,并且为每个这样的对识别N个最长路径。

    Speed-path debug using at-speed scan test patterns
    22.
    发明授权
    Speed-path debug using at-speed scan test patterns 有权
    使用速度扫描测试模式的速度路径调试

    公开(公告)号:US08468409B2

    公开(公告)日:2013-06-18

    申请号:US12634682

    申请日:2009-12-09

    IPC分类号: G01R31/28

    摘要: Speed-path debug techniques based on at-speed scan test patterns. Potential speed paths are identified based upon detected at-speed scan pattern failures and unknown X-value simulation. When the number of identified speed paths is large, the suspect speed paths are ranked.

    摘要翻译: 基于速度扫描测试模式的速度路径调试技术。 基于检测到的高速扫描模式故障和未知的X值模拟识别潜在速度路径。 当识别的速度路径数量大时,可疑速度路径被排序。

    Speed-Path Debug Using At-Speed Scan Test Patterns
    23.
    发明申请
    Speed-Path Debug Using At-Speed Scan Test Patterns 有权
    使用速度扫描测试模式的速度路径调试

    公开(公告)号:US20100185908A1

    公开(公告)日:2010-07-22

    申请号:US12634682

    申请日:2009-12-09

    IPC分类号: G01R31/3177 G06F11/25

    摘要: Speed-path debug techniques based on at-speed scan test patterns. Potential speed paths are identified based upon detected at-speed scan pattern failures and unknown X-value simulation. When the number of identified speed paths is large, the suspect speed paths are ranked.

    摘要翻译: 基于速度扫描测试模式的速度路径调试技术。 基于检测到的高速扫描模式故障和未知的X值模拟识别潜在速度路径。 当识别的速度路径数量大时,可疑速度路径被排序。

    Timing Failure Debug
    24.
    发明申请
    Timing Failure Debug 审中-公开
    定时故障调试

    公开(公告)号:US20110035638A1

    公开(公告)日:2011-02-10

    申请号:US12420047

    申请日:2009-04-07

    申请人: Ruifeng Guo

    发明人: Ruifeng Guo

    IPC分类号: G01R31/3177 G06F11/25

    CPC分类号: G01R31/318547

    摘要: A debug flow that uses debug-friendly test patterns and logic fault diagnosis techniques to help physical fault isolation of timing failures.

    摘要翻译: 调试流程,使用调试友好的测试模式和逻辑故障诊断技术来帮助定时故障的物理故障隔离。