公开(公告)号：US5455803A

公开(公告)日：1995-10-03

申请号：US231677

申请日：1994-04-25

申请人： Yukinori Kodama

发明人： Yukinori Kodama

IPC分类号： G11C11/407 ,  G11C7/22 ,  G11C8/18 ,  G11C11/409 ,  G11C8/00

CPC分类号： G11C7/22 ,  G11C8/18

摘要： A semiconductor memory device includes a memory cell array, an address part for supplying address signals to the memory cell array, a read/write part for reading data from the memory cell array and writing data into the memory cell array, and an internal clock signal generating circuit for generating an internal clock signal from an external clock signal. The internal clock signal has a cycle with an active-level portion of constant duration independent of a frequency of the external clock signal and is output, as a timing signal, to predetermined structural parts of the address part and/or the read/write part.

摘要翻译： 半导体存储器件包括存储单元阵列，用于向存储单元阵列提供地址信号的地址部分，用于从存储单元阵列读取数据并将数据写入存储单元阵列的读/写部分，以及内部时钟信号 产生电路，用于从外部时钟信号产生内部时钟信号。 内部时钟信号具有与外部时钟信号的频率无关的具有恒定持续时间的有效电平部分的周期，并且作为定时信号输出到地址部分和/或读取/写入部分的预定结构部分 。

公开(公告)号：US5384726A

公开(公告)日：1995-01-24

申请号：US193535

申请日：1994-02-08

申请人： Hiroyoshi Tomita ,  Makoto Yanagisawa ,  Yukinori Kodama

发明人： Hiroyoshi Tomita ,  Makoto Yanagisawa ,  Yukinori Kodama

IPC分类号： G11C7/06 ,  G11C5/06

CPC分类号： G11C7/065

摘要： A semiconductor memory device includes a memory cell array in which a number of sense amplifiers are provided, a plurality of segmented drive lines each connected to a group of sense amplifiers for driving the same, each of the segmented drive lines being formed of first and second drive line segments forming a pair, and a number of trunks for supplying electric power to the segmented drive lines. Each of the trunks includes a first conductor strip extending from a first side of the memory cell array toward a second side for connection to a plurality of the first drive line segments upon crossing the same, and a second conductor strip extending from the second side of the memory cell array toward the first side for connection to a plurality of the second drive line segments upon crossing the same. The first and second conductor strips have distal end parts having a reduced width and a mutually complementary shape, such that the first and second conductor strips are disposed to form a straight strip having a substantially constant width throughout the memory cell array.

摘要翻译： 一种半导体存储器件包括其中提供多个读出放大器的存储单元阵列，多个分段驱动线，每个驱动线连接到用于驱动读出放大器的一组读出放大器，每个分段驱动线由第一和第二 形成一对的驱动线段和用于向分段驱动线提供电力的多个中继线。 每个中继线包括从存储单元阵列的第一侧向第二侧延伸的第一导体条，用于在与第一驱动线段交叉时与多个第一驱动线段连接，第二导体条从第二侧延伸 所述存储单元阵列朝向所述第一侧，用于在与所述第二驱动线段交叉时连接到所述第二驱动线段。 第一和第二导体条具有具有减小的宽度和相互互补形状的远端部分，使得第一和第二导体条被设置成形成整个存储单元阵列具有基本恒定的宽度的直条。