公开(公告)号：US20090287867A1

公开(公告)日：2009-11-19

申请号：US12432896

申请日：2009-04-30

申请人： Jun Takehara ,  Naruhiko Aramaki ,  Toshikazu Kawamura ,  Yoshito Sameda ,  Hiroshi Nakatani ,  Motohiko Okabe ,  Yukitaka Yoshida

发明人： Jun Takehara ,  Naruhiko Aramaki ,  Toshikazu Kawamura ,  Yoshito Sameda ,  Hiroshi Nakatani ,  Motohiko Okabe ,  Yukitaka Yoshida

IPC分类号： G06F13/40

CPC分类号： G06F11/0793 ,  G06F11/0745

摘要： A memory control unit controls writing and reading of data to the slave device according to an instruction from the master device. A bus diagnosis line is directly connected from the bus signal control circuit to a bus signal receiving terminal of the slave device without passing through the address bus and the control signal line. A bus signal abnormality processing unit compares an output bus signal output from the bus signal control circuit to the address bus and the control signal line with a feedback bus signal fed back through the bus diagnosis line to determine the presence/absence of a difference. The memory control unit elongates a bus cycle period of a bus cycle of operation being executed when it is determined in the bus signal abnormality processing unit that the difference is present.

摘要翻译： 存储器控制单元根据来自主设备的指令控制对从设备的数据的写入和读取。 总线诊断线从总线信号控制电路直接连接到从设备的总线信号接收终端，而不通过地址总线和控制信号线。 总线信号异常处理单元将从总线信号控制电路输出的输出总线信号与地址总线和控制信号线进行比较，其中反馈总线信号通过总线诊断线反馈，以确定差异的存在/不存在。 当在总线信号异常处理单元中确定存在差异时，存储器控制单元延长正在执行的总线周期的总线周期。