公开(公告)号：US20090287867A1

公开(公告)日：2009-11-19

申请号：US12432896

申请日：2009-04-30

申请人： Jun Takehara ,  Naruhiko Aramaki ,  Toshikazu Kawamura ,  Yoshito Sameda ,  Hiroshi Nakatani ,  Motohiko Okabe ,  Yukitaka Yoshida

发明人： Jun Takehara ,  Naruhiko Aramaki ,  Toshikazu Kawamura ,  Yoshito Sameda ,  Hiroshi Nakatani ,  Motohiko Okabe ,  Yukitaka Yoshida

IPC分类号： G06F13/40

CPC分类号： G06F11/0793 ,  G06F11/0745

摘要： A memory control unit controls writing and reading of data to the slave device according to an instruction from the master device. A bus diagnosis line is directly connected from the bus signal control circuit to a bus signal receiving terminal of the slave device without passing through the address bus and the control signal line. A bus signal abnormality processing unit compares an output bus signal output from the bus signal control circuit to the address bus and the control signal line with a feedback bus signal fed back through the bus diagnosis line to determine the presence/absence of a difference. The memory control unit elongates a bus cycle period of a bus cycle of operation being executed when it is determined in the bus signal abnormality processing unit that the difference is present.

摘要翻译： 存储器控制单元根据来自主设备的指令控制对从设备的数据的写入和读取。 总线诊断线从总线信号控制电路直接连接到从设备的总线信号接收终端，而不通过地址总线和控制信号线。 总线信号异常处理单元将从总线信号控制电路输出的输出总线信号与地址总线和控制信号线进行比较，其中反馈总线信号通过总线诊断线反馈，以确定差异的存在/不存在。 当在总线信号异常处理单元中确定存在差异时，存储器控制单元延长正在执行的总线周期的总线周期。

公开(公告)号：US08131900B2

公开(公告)日：2012-03-06

申请号：US12432896

申请日：2009-04-30

申请人： Jun Takehara ,  Naruhiko Aramaki ,  Toshikazu Kawamura ,  Yoshito Sameda ,  Hiroshi Nakatani ,  Motohiko Okabe ,  Yukitaka Yoshida

发明人： Jun Takehara ,  Naruhiko Aramaki ,  Toshikazu Kawamura ,  Yoshito Sameda ,  Hiroshi Nakatani ,  Motohiko Okabe ,  Yukitaka Yoshida

IPC分类号： G06F13/00 ,  H04L1/14

CPC分类号： G06F11/0793 ,  G06F11/0745

摘要： A memory control unit controls writing and reading of data to the slave device according to an instruction from the master device. A bus diagnosis line is directly connected from the bus signal control circuit to a bus signal receiving terminal of the slave device without passing through the address bus and the control signal line. A bus signal abnormality processing unit compares an output bus signal output from the bus signal control circuit to the address bus and the control signal line with a feedback bus signal fed back through the bus diagnosis line to determine the presence/absence of a difference. The memory control unit elongates a bus cycle period of a bus cycle of operation being executed when it is determined in the bus signal abnormality processing unit that the difference is present.

摘要翻译： 存储器控制单元根据来自主设备的指令控制对从设备的数据的写入和读取。 总线诊断线从总线信号控制电路直接连接到从设备的总线信号接收终端，而不通过地址总线和控制信号线。 总线信号异常处理单元将从总线信号控制电路输出的输出总线信号与地址总线和控制信号线进行比较，其中反馈总线信号通过总线诊断线反馈，以确定差异的存在/不存在。 当在总线信号异常处理单元中确定存在差异时，存储器控制单元延长正在执行的总线周期的总线周期。

公开(公告)号：US08281203B2

公开(公告)日：2012-10-02

申请号：US12751303

申请日：2010-03-31

申请人： Masayuki Murakami ,  Jun Takehara ,  Naruhiko Aramaki ,  Toshikazu Kawamura ,  Yoichi Takayanagi ,  Motohiko Okabe

发明人： Masayuki Murakami ,  Jun Takehara ,  Naruhiko Aramaki ,  Toshikazu Kawamura ,  Yoichi Takayanagi ,  Motohiko Okabe

IPC分类号： G08C25/02

CPC分类号： G06F13/4282

摘要： When a transaction layer circuit detects an error, error information in respect of transmission data is set in a TLP digest. The method includes: a step in which, at an endpoint (3a) that receives a memory read request transmitted by the root complex 1, if an error is detected during transmission of first data corresponding to the requested TLP, error information is set in the TLP digest and a completion with data attached is returned; a step in which the root complex (1) returns a memory read request based on the error information to the endpoint; a step in which the endpoint returns requested second data; and a step in which the root complex terminates the response after overwriting the error location of the first data that was held, with the second data.

公开(公告)号：US20100251055A1

公开(公告)日：2010-09-30

申请号：US12751303

申请日：2010-03-31

申请人： Masayuki Murakami ,  Jun Takehara ,  Naruhiko Aramaki ,  Toshikazu Kawamura ,  Yoichi Takayanagi ,  Motohiko Okabe

发明人： Masayuki Murakami ,  Jun Takehara ,  Naruhiko Aramaki ,  Toshikazu Kawamura ,  Yoichi Takayanagi ,  Motohiko Okabe

IPC分类号： H04L1/18

CPC分类号： G06F13/4282

摘要： When a transaction layer circuit detects an error, error information in respect of transmission data is set in a TLP digest. The method includes: a step in which, at an endpoint (3a) that receives a memory read request transmitted by the root complex 1, if an error is detected during transmission of first data corresponding to the requested TLP, error information is set in the TLP digest and a completion with data attached is returned; a step in which the root complex (1) returns a memory read request based on the error information to the endpoint; a step in which the endpoint returns requested second data; and a step in which the root complex terminates the response after overwriting the error location of the first data that was held, with the second data.

摘要翻译： 当事务层电路检测到错误时，在TLP摘要中设置关于传输数据的错误信息。 该方法包括：在接收由根复合体1发送的存储器读取请求的端点（3a）的步骤中，如果在发送与所请求的TLP相对应的第一数据的传输期间检测到错误，则将错误信息设置在 返回TLP摘要和附带数据的完成; 根复合体（1）将基于错误信息的存储器读取请求返回到端点的步骤; 端点返回请求的第二数据的步骤; 以及其中根复合体在用第二数据覆盖保持的第一数据的错误位置之后终止响应的步骤。

公开(公告)号：US20120030402A1

公开(公告)日：2012-02-02

申请号：US13272265

申请日：2011-10-13

申请人： Masayuki MURAKAMI ,  Jun Takehara ,  Naruhiko Aramaki ,  Toshikazu Kawamura ,  Yoichi Takayanagi ,  Motohiko Okabe

发明人： Masayuki MURAKAMI ,  Jun Takehara ,  Naruhiko Aramaki ,  Toshikazu Kawamura ,  Yoichi Takayanagi ,  Motohiko Okabe

IPC分类号： G06F13/20

CPC分类号： H04L1/0045 ,  H04L1/0061 ,  H04L2001/0097

摘要： A PCI Express TLP processing circuit (10) comprises: a plurality of reception processing sections (2a1); a transmission processing section (2b); and a multiplexer (2c1) that performs transmission to the transmission processing section, selecting one of the reception processing sections; and at least a reception processing section comprises: a redundancy code generating circuit (12); an LCRC/sequential number detection circuit (13); a buffer memory (14); a packet control circuit section (16) that controls transmission for normal transmission to the transmission destination of the TLP in question or for nullifying transmission; and the transmission processing section comprises: a sequential number generating circuit (19); an LCRC generating circuit (20) and a relay circuit error detection circuit (21), whereby data integrity of the transmitted TLP can be guaranteed.

摘要翻译： PCI Express TLP处理电路（10）包括：多个接收处理部分（2a1）; 发送处理部（2b）; 以及多路复用器（2c1），其向所述发送处理部进行发送，选择所述接收处理部中的一个; 并且至少一个接收处理部分包括：冗余码产生电路（12）; LCRC /序列号检测电路（13）; 缓冲存储器（14）; 分组控制电路部分（16），其控制用于正常传输到所讨论的TLP的传输目的地的传输或用于无效传输; 并且所述发送处理部分包括：序列号产生电路（19）; LCRC生成电路（20）和继电器电路错误检测电路（21），能够保证发送的TLP的数据完整性。