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公开(公告)号：US09009692B2
公开(公告)日：2015-04-14
申请号：US12647484
申请日：2009-12-26
IPC分类号： G06F9/45
CPC分类号： G06F8/441
摘要： A system and method for minimizing register spills during compilation. A compiler reallocates spilled variables from stack memory to other available registers. Although a corresponding register file may not have available registers for storage, the compiler identifies available registers in other locations for storage. The compiler identifies available registers in an alternate register file, wherein the alternate register file may be a floating-point register file which is then used for spilled integer variables. Other instruction type combinations between spilled variables and alternate register files are possible. When an available register within the alternate register file is identified, the compiler modifies the program instructions to allocate the corresponding spilled variable to the available register.
摘要翻译： 一种用于在编译期间最小化寄存器溢出的系统和方法。 编译器将溢出的变量从堆栈内存重新分配给其他可用的寄存器。 虽然相应的寄存器文件可能没有可用的存储寄存器，但编译器可以识别其他位置的可用寄存器进行存储。 编译器识别备用寄存器文件中的可用寄存器，其中备用寄存器文件可以是浮点寄存器文件，然后用于溢出的整数变量。 溢出变量和备用寄存器文件之间的其他指令类型组合是可能的。 当识别备用寄存器文件中的可用寄存器时，编译器会修改程序指令，将相应的溢出变量分配给可用的寄存器。
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公开(公告)号：US08959493B2
公开(公告)日：2015-02-17
申请号：US13169954
申请日：2011-06-27
申请人： David J. Harman , Brian Johnson , David Knibb , Andrew Wright
发明人： David J. Harman , Brian Johnson , David Knibb , Andrew Wright
IPC分类号： G06F9/45
摘要： Embodiments of the present invention provide a method, system and computer program product for USING range validation during assembly of an assembly language program. In an embodiment of the invention, a method for USING range validation during assembly of an assembly language program has been provided. The method can include parsing assembler language source code loaded for assembly in an assembler executing in memory of a computer. The method also can include identifying a USING statement in the source code establishing a base address as the content of a register. Finally, in response to additionally identifying a subsequent statement in the source code that modifies the content of the register, a warning of an invalid USING range can be generated.
摘要翻译： 本发明的实施例提供了一种用于在组装语言程序的组装期间使用范围验证的方法，系统和计算机程序产品。 在本发明的一个实施例中，提供了一种在组装语言程序的组装期间使用范围验证的方法。 该方法可以包括对在计算机的存储器中执行的汇编器中装载的汇编语言源代码进行解析。 该方法还可以包括在建立基地址的源代码中标识USING语句作为寄存器的内容。 最后，响应于另外识别修改寄存器内容的源代码中的后续语句，可以生成无效的使用范围的警告。
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公开(公告)号：US08904367B1
公开(公告)日：2014-12-02
申请号：US13803689
申请日：2013-03-14
申请人： The MathWorks, Inc.
发明人： Partha Biswas , Vijaya Raghavan , Zhihong Zhao
IPC分类号： G06F9/45
CPC分类号： G06F9/44557 , G06F8/441 , G06F8/4451 , G06F17/505 , G06F17/5072
摘要： A system and method automatically inserts pipelines into a high-level program specification. An Intermediate Representation (IR) builder creates one or more graphs or trees based on the high-level program specification. A scheduler iteratively applies a bounded scheduling algorithm to produce an execution schedule for the IR minimizing overall execution time for a given number of pipeline stages. A Hardware Description Language (HDL) code generator may utilize the pipelined, scheduled IR to generate optimized HDL code corresponding to the high-level program specification. An annotated version of the high-level program specification showing where the pipelines have been inserted may be displayed allowing additional design exploration.
摘要翻译： 系统和方法将管道自动插入到高级程序规范中。 中间表示（IR）构建器基于高级程序规范创建一个或多个图形或树。 调度器迭代地应用有界调度算法来产生用于IR的执行调度，使给定数量的流水线级的总体执行时间最小化。 硬件描述语言（HDL）代码生成器可以利用流水线计划的IR来产生对应于高级程序规范的优化的HDL代码。 显示管道插入位置的高级程序规范的注释版本可以被显示，允许额外的设计探索。
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公开(公告)号：US20130305231A1
公开(公告)日：2013-11-14
申请号：US13942846
申请日：2013-07-16
IPC分类号： G06F9/45
摘要： A system is provided for splitting a live-range of a variable in frequently executed regions of program instructions. The live-range of a variable is split into multiple sub-ranges, each of which can be assigned to a different register or spilled into memory. The amount of spill code is reduced in frequently used regions of code by coalescing the live ranges based on profile information obtained after splitting the live ranges at every join and fork point in a control flow graph.
摘要翻译： 提供了一种用于在频繁执行的程序指令区域中分割变量的实时范围的系统。 变量的实时范围被分成多个子范围，每个子范围可以分配给不同的寄存器或溢出到存储器中。 在频繁使用的代码区域中，通过在控制流程图中的每个连接点和分支点分割活动范围之后获得的简档信息来聚合生存范围，减少了经常使用的代码区域的数量。
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公开(公告)号：US08578358B2
公开(公告)日：2013-11-05
申请号：US13298764
申请日：2011-11-17
申请人： Jeffry E. Gonion
发明人： Jeffry E. Gonion
IPC分类号： G06F9/45
摘要： A macroscalar processor architecture is described herein. In one embodiment, a processor receives instructions of a program loop having a vector block and a sequence block intended to be executed after the vector block, where the processor includes multiple slices and each of the slices is capable of executing an instruction of an iteration of the program loop substantially in parallel. For each iteration of the program loop, the processor executes an instruction of the sequence block using one of the slices while executing instructions of the vector block using a remainder of the slices substantially in parallel. Other methods and apparatuses are also described.
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26.发明授权Conflict-free register allocation using a multi-bank register file with input operand alignment 有权使用输入操作数对齐的多存储器寄存器文件进行无冲突寄存器分配公开(公告)号：US08555035B1
公开(公告)日：2013-10-08
申请号：US12831953
申请日：2010-07-07
申请人： Anjul Patney , William J. Dally
发明人： Anjul Patney , William J. Dally
IPC分类号： G06F9/44
CPC分类号： G06F8/441
摘要： One embodiment of the present invention sets forth a technique for using a multi-bank register file that reduces the size of or eliminates a switch and/or staging registers that are used to gather input operands for instructions. Each function unit input may be directly connected to one bank of the multi-bank register file with neither a switch nor a staging register. A compiler or register allocation unit ensures that the register file accesses for each instruction are conflict-free (no instruction can access the same bank more than once in the same cycle). The compiler or register allocation unit may also ensure that the register file accesses for each instruction are also aligned (each input of a function unit can only come from the bank connected to that input).
摘要翻译： 本发明的一个实施例提出了一种使用减少用于收集用于指令的输入操作数的开关和/或分段寄存器的大小或消除的多存储体寄存器堆的技术。 每个功能单元输入可以直接连接到多存储区寄存器文件的一行，既不带有开关也不是暂存寄存器。 编译器或寄存器分配单元确保每个指令的寄存器文件访问是无冲突的（没有指令可以在同一周期内多次访问同一个存储体）。 编译器或寄存器分配单元还可以确保每个指令的寄存器文件访问也被对齐（功能单元的每个输入只能来自连接到该输入的存储体）。
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27.发明授权Eliminating redundant operations for common properties using shared real registers 有权使用共享实际寄存器消除普通属性的冗余操作公开(公告)号：US08448157B2
公开(公告)日：2013-05-21
申请号：US12912045
申请日：2010-10-26
IPC分类号： G06F9/45
CPC分类号： G06F8/441
摘要： One embodiment of a method for eliminating redundant operations establishing common properties includes identifying a first virtual register storing a first value having a common property. The method may assign the first virtual register to use a real register. The method may further identify a second virtual register storing a second value also having the common property. The method may assign the second virtual register to use the same real register after the first value is no longer live. As a result of assigning the second virtual register to the first real register, the method may eliminate an operation configured to establish the common property for the second virtual register since this operation is redundant and is no longer needed.
摘要翻译： 用于消除建立公共属性的冗余操作的方法的一个实施例包括识别存储具有共同属性的第一值的第一虚拟寄存器。 该方法可以分配第一个虚拟寄存器以使用实际寄存器。 该方法还可以识别存储具有共同属性的第二值的第二虚拟寄存器。 该方法可以在第一个值不再存活之后将第二个虚拟寄存器分配给使用相同的实际寄存器。 作为将第二虚拟寄存器分配给第一实际寄存器的结果，该方法可以消除配置为为第二虚拟寄存器建立公共属性的操作，因为该操作是冗余的并且不再需要。
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28.发明授权公开(公告)号：US08379032B2
公开(公告)日：2013-02-19
申请号：US11864484
申请日：2007-09-28
申请人： Lin Chen , Junhong Sun , Guofang Jiao , Chihong Zhang , Lingjun Chen
发明人： Lin Chen , Junhong Sun , Guofang Jiao , Chihong Zhang , Lingjun Chen
IPC分类号： G06F15/00
CPC分类号： G06T15/005 , G06F8/441
摘要： The present disclosure includes system and method of mapping shader variables into physical registers. In an embodiment, a graphics processing unit (GPU) and a memory coupled to the GPU are disclosed. The memory includes a processor readable data file that has a register file portion. The register file portion has a rectangular structure including a plurality of data items. At least two of the plurality of data items corresponding to data elements of a shader program. The data elements have different data storage types.
摘要翻译： 本公开包括将着色器变量映射到物理寄存器的系统和方法。 在一个实施例中，公开了一种图形处理单元（GPU）和耦合到GPU的存储器。 存储器包括具有寄存器文件部分的处理器可读数据文件。 寄存器文件部分具有包括多个数据项的矩形结构。 与着色器程序的数据元素对应的多个数据项中的至少两个。 数据元素具有不同的数据存储类型。
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29.发明申请公开(公告)号：US20130019060A1
公开(公告)日：2013-01-17
申请号：US13182608
申请日：2011-07-14
申请人： Tim J. WILKENS , Michael C. BERG
发明人： Tim J. WILKENS , Michael C. BERG
IPC分类号： G06F12/08
CPC分类号： G06F8/441
摘要： A device identifies array accesses of variables in a program code that includes multiple arrays, and identifies array access patterns for one of the array accesses. The device also determines an order of the array access patterns identified for the array accesses, and calculates, based on the order, distances between the array access patterns. The device further shares address calculations amongst the array accesses associated with array access patterns with one or more of the distances that are equivalent.
摘要翻译： 设备识别包含多个数组的程序代码中变量的数组访问，并识别阵列访问之一的数组访问模式。 设备还确定为阵列访问所标识的阵列访问模式的顺序，并且基于顺序来计算阵列访问模式之间的距离。 该设备进一步与阵列访问模式相关联的阵列访问中的一个或多个距离相等的地址计算。
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公开(公告)号：US20120331446A1
公开(公告)日：2012-12-27
申请号：US13169954
申请日：2011-06-27
申请人： David J. Harman , Brian Johnson , David Knibb , Andrew Wright
发明人： David J. Harman , Brian Johnson , David Knibb , Andrew Wright
IPC分类号： G06F9/44
摘要： Embodiments of the present invention provide a method, system and computer program product for USING range validation during assembly of an assembly language program. In an embodiment of the invention, a method for USING range validation during assembly of an assembly language program has been provided. The method can include parsing assembler language source code loaded for assembly in an assembler executing in memory of a computer. The method also can include identifying a USING statement in the source code establishing a base address as the content of a register. Finally, in response to additionally identifying a subsequent statement in the source code that modifies the content of the register, a warning of an invalid USING range can be generated.
摘要翻译： 本发明的实施例提供了一种用于在组装语言程序的组装期间使用范围验证的方法，系统和计算机程序产品。 在本发明的一个实施例中，提供了一种在组装语言程序的组装期间使用范围验证的方法。 该方法可以包括对在计算机的存储器中执行的汇编器中装载的汇编语言源代码进行解析。 该方法还可以包括在建立基地址的源代码中标识USING语句作为寄存器的内容。 最后，响应于另外识别修改寄存器内容的源代码中的后续语句，可以生成无效的使用范围的警告。
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