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    Photomultiplier circuit including means for rapidly reducing the sensitivity thereof
    21.
    发明授权
    Photomultiplier circuit including means for rapidly reducing the sensitivity thereof 失效
    照相机电路，包括快速降低其灵敏度的手段

    公开(公告)号：US3821546A

    公开(公告)日：1974-06-28

    申请号：US31019372

    申请日：1972-11-28

    Applicant: NASA

    Inventor： MC CLENAHAN J

    IPC: H01J43/04 ,  H01J39/12

    CPC classification number: H01J43/04

    Abstract: A photomultiplier tube comprising a plurality of electrodes including a light sensitive cathode, an anode, and a plurality of dynodes positioned in space-apart manner along the electron beam path between the cathode and anode and having a power supply and a voltage divider for supplying bias voltages across each successive pair of electrodes along the beam path, at least one switching device being provided across a pair of said electrodes, preferably across the cathode and first dynode or across the first and second dynodes, which, when activated, will rapidly reduce the bias voltage across the associated pair of electrodes to near zero, thereby substantially reducing the sensitivity of the multiplier to protect it from the effects of excessive light intensity input. In a preferred embodiment of the invention, an SCR is coupled across the cathode and first dynode and is operated by a blanking or trigger pulse applied to its control gate to rapidly reduce the bias voltage across this first stage. Additional switching rectifiers may be employed across other stages of the multiplier to insure the desired reduction in sensitivity.

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