公开(公告)号：US20120215973A1

公开(公告)日：2012-08-23

申请号：US13460496

申请日：2012-04-30

申请人： Brian J. Cagno ,  John C. Elliott ,  Gregg S. Lucas ,  Andrew D. Walls

发明人： Brian J. Cagno ,  John C. Elliott ,  Gregg S. Lucas ,  Andrew D. Walls

IPC分类号： G06F12/00

CPC分类号： G06F11/2094 ,  G06F11/2089 ,  G06F11/2092 ,  G06F11/2097

摘要： A solid state drive includes a first solid state disc controller (SSDC), a second SSDC and a flash array. The flash array includes a first flash port and a second flash port. The first SSDC is configured to connect to the flash array through the first flash port and the second flash array is configured to connect to the flash array through the second flash port. The first SSDC and the second SSDC are both configured to connect to all memory within the flash array and the first SSDC, second SSDC, and flash array are within a common solid state drive.

摘要翻译： 固态驱动器包括第一固态盘控制器（SSDC），第二SSDC和闪存阵列。 闪存阵列包括第一闪存端口和第二闪存端口。 第一个SSDC配置为通过第一个闪存端口连接到闪存阵列，第二个闪存阵列被配置为通过第二个闪存端口连接到闪存阵列。 第一个SSDC和第二个SSDC都配置为连接到闪存阵列中的所有内存，而第一个SSDC，第二个SSDC和闪存阵列位于公共固态驱动器内。

公开(公告)号：US08040750B2

公开(公告)日：2011-10-18

申请号：US12145969

申请日：2008-06-25

申请人： Brian J. Cagno ,  John C. Elliott ,  Gregg S. Lucas

发明人： Brian J. Cagno ,  John C. Elliott ,  Gregg S. Lucas

IPC分类号： G11C5/14

CPC分类号： G11C5/141

摘要： A controller of a memory system is configured to reduce power requirements during memory backup transition. When transitioning to backup mode, the memory system controller performs a number of power saving techniques. The controller may change a number of configuration settings in the volatile memory system, such as reducing output driver strength, increasing differential impedance, increasing on-die termination, disabling receiver input circuitry, and disconnecting the termination voltage network. The controller may also assert a hard reset to the storage controller system to significantly reduce the load and allow the voltage regulator to continue to provide power to the memory system for a longer period of time.

摘要翻译： 存储器系统的控制器被配置为在存储器备份转换期间减少功率需求。 当转换到备份模式时，存储系统控制器执行许多省电技术。 控制器可以改变易失性存储器系统中的多个配置设置，例如降低输出驱动器强度，增加差分阻抗，增加片上端接，禁用接收器输入电路以及断开终端电压网络。 控制器还可以向存储控制器系统断言硬复位以显着地减少负载，并允许电压调节器持续更长时间地向存储器系统供电。

公开(公告)号：US20090254772A1

公开(公告)日：2009-10-08

申请号：US12099373

申请日：2008-04-08

申请人： Brian J. Cagno ,  John C. Elliott ,  Robert A. Kubo ,  Gregg S. Lucas

发明人： Brian J. Cagno ,  John C. Elliott ,  Robert A. Kubo ,  Gregg S. Lucas

IPC分类号： G06F1/28 ,  G11C5/14

CPC分类号： G06F1/28 ,  G11C5/141 ,  G11C11/4074

摘要： A memory system has mechanisms for scavenging capacity of a super capacitor by removing, or reducing, system load from the super capacitor when the super capacitor voltage decays below a low threshold. The mechanisms then restore the system load to the super capacitor when the super capacitor voltage ramps back above a high threshold. A controller may reduce system load by placing a volatile memory system in a standby state and disabling a field effect transistor to remove power from a non-volatile memory system. A controller may adjust the high threshold and/or a low threshold by setting a digitally controlled potentiometer in a threshold detect circuit via an I2C bus.

摘要翻译： 存储器系统具有通过在超级电容器电压降低到低阈值以下时从超级电容器中去除或降低系统负载来清除超级电容器容量的机制。 当超级电容器电压升高到高阈值以上时，机制将系统负载恢复到超级电容器。 控制器可以通过将易失性存储器系统置于待机状态并且禁用场效应晶体管来从非易失性存储器系统去除功率来降低系统负载。 控制器可以通过经由I2C总线在门限检测电路中设置数字控制的电位器来调节高阈值和/或低阈值。

公开(公告)号：US07558039B2

公开(公告)日：2009-07-07

申请号：US11737418

申请日：2007-04-19

申请人： Brian J. Cagno ,  John C. Elliott

发明人： Brian J. Cagno ,  John C. Elliott

IPC分类号： H02H9/02

CPC分类号： H02H9/004

摘要： Detecting excess current flow in a pluggable component is performed by completing a first current supply path between a power source and a pluggable component, and subsequently completing a second current supply path in parallel with the first current supply path. The first and second current supply paths form a current divider for supplying the pluggable component with electrical power from the power source. The first current supply path includes a current sensing mechanism for sensing current consumption of the pluggable component. The sensed current consumption is used to provide excess current detection for the pluggable component.

摘要翻译： 通过完成电源和可插拔部件之间的第一电流供应路径，随后完成与第一电流供应路径并联的第二电流供应路径，来检测可插拔部件中的过电流。 第一和第二电流供应路径形成分流器，用于向可插拔部件提供来自电源的电力。 第一电流供应路径包括用于感测可插拔部件的电流消耗的电流检测机构。 感测的电流消耗用于为可插拔部件提供过电流检测。

公开(公告)号：US20080259514A1

公开(公告)日：2008-10-23

申请号：US11737418

申请日：2007-04-19

申请人： Brian J. Cagno ,  John C. Elliott

发明人： Brian J. Cagno ,  John C. Elliott

IPC分类号： H02H3/08

CPC分类号： H02H9/004

摘要： Detecting excess current flow in a pluggable component is performed by completing a first current supply path between a power source and a pluggable component, and subsequently completing a second current supply path in parallel with the first current supply path. The first and second current supply paths form a current divider for supplying the pluggable component with electrical power from the power source. The first current supply path includes a current sensing mechanism for sensing current consumption of the pluggable component. The sensed current consumption is used to provide excess current detection for the pluggable component.

摘要翻译： 通过完成电源和可插拔部件之间的第一电流供应路径，随后完成与第一电流供应路径并联的第二电流供应路径，来检测可插拔部件中的过电流。 第一和第二电流供应路径形成分流器，用于向可插拔部件提供来自电源的电力。 第一电流供应路径包括用于感测可插拔部件的电流消耗的电流检测机构。 感测的电流消耗用于为可插拔部件提供过电流检测。

公开(公告)号：US07428623B2

公开(公告)日：2008-09-23

申请号：US11145386

申请日：2005-06-03

申请人： Brian J. Cagno ,  Robert A. Kubo ,  Gregg S. Lucas

发明人： Brian J. Cagno ,  Robert A. Kubo ,  Gregg S. Lucas

IPC分类号： G06F13/00 ,  G06F12/00

CPC分类号： H04L25/03878

摘要： A method is disclosed to set signal compensation settings for a data storage device comprising a first port and a second port, where that first port is interconnected to a first switch via a first communication pathway having a predetermined first length. The method determines first signal compensation settings based upon the first length.

摘要翻译： 公开了一种为包括第一端口和第二端口的数据存储设备设置信号补偿设置的方法，其中第一端口经由具有预定第一长度的第一通信路径与第一开关互连。 该方法基于第一长度来确定第一信号补偿设置。

公开(公告)号：US20080018313A1

公开(公告)日：2008-01-24

申请号：US11458750

申请日：2006-07-20

申请人： Brian J. Cagno ,  John C. Elliott ,  Enrique Q. Garcia

发明人： Brian J. Cagno ,  John C. Elliott ,  Enrique Q. Garcia

IPC分类号： G05F1/00

CPC分类号： H02M1/15 ,  H02M2001/008

摘要： A power supply system for reducing input ripple voltage, the system including: a first switching regulator having at least two input pins, one input pin being a voltage input pin and another input pin being a synchronization input pin; a second switching regulator having at least two input pins, one input pin being a voltage input pin and another input pin being a synchronization input pin; wherein outputs of the first switching regulator and the second switching regulator are connected to a power bus; a first delay element connected to the synchronization input pin of the first switching regulator; a second delay element connected to the synchronization input pin of the second switching regulator; wherein the first delay element and the second delay element have different delays, the first switching regulator and second switching regulator operating out of phase; and a master clock for providing timing control to the first and second delay elements.

摘要翻译： 一种用于减小输入纹波电压的电源系统，该系统包括：具有至少两个输入引脚的第一开关调节器，一个输入引脚是电压输入引脚，另一个输入引脚是同步输入引脚; 具有至少两个输入引脚的第二开关调节器，一个输入引脚是电压输入引脚，另一个输入引脚是同步输入引脚; 其中所述第一开关调节器和所述第二开关调节器的输出端连接到电源总线; 连接到第一开关调节器的同步输入引脚的第一延迟元件; 连接到第二开关调节器的同步输入引脚的第二延迟元件; 其中所述第一延迟元件和所述第二延迟元件具有不同的延迟，所述第一开关调节器和第二开关调节器异相工作; 以及用于向第一和第二延迟元件提供定时控制的主时钟。

公开(公告)号：US07281070B2

公开(公告)日：2007-10-09

申请号：US11045682

申请日：2005-01-28

申请人： Matthew D. Bomhoff ,  Brian J. Cagno ,  Robert A. Kubo ,  Gregg S. Lucas

发明人： Matthew D. Bomhoff ,  Brian J. Cagno ,  Robert A. Kubo ,  Gregg S. Lucas

IPC分类号： G06F12/00 ,  G06F11/00 ,  H04J3/24 ,  G06F15/16

CPC分类号： G06F13/4286 ,  Y02D10/14 ,  Y02D10/151

摘要： A multiple-master Inter Integrated Circuit (“I2C”) bus system includes a first master device including a first processing device within a first power boundary and a second master device including a second processing device within a second power boundary connected through a single I2C bus to one or more slave devices. The second master device utilizes a software algorithm or hardware component to detect or manage power up of the first power boundary. Additionally, the second master device includes a bus control algorithm that allows it, once initiated, to communicate with the connected slave device, to direct the first power boundary to activate or detect that the first power boundary has powered up, and to release the I2C bus. Once the first processor has initialized, the first master device acquires control of the I2C bus without arbitration or interference with the second master device.

摘要翻译： 多主集成电路（“I2C”）总线系统包括第一主设备，其包括第一电源边界内的第一处理设备和第二主设备，第二主设备包括通过单个连接的第二电源边界内的第二处理设备 I 2 C总线到一个或多个从设备。 第二主设备利用软件算法或硬件组件来检测或管理第一功率边界的上电。 此外，第二主设备包括总线控制算法，其允许其一旦被启动与所连接的从设备进行通信，以引导第一功率边界来激活或检测到第一功率边界已通电，并释放I 2 C总线。 一旦第一处理器被初始化，第一主设备获得对I2C总线的控制，而不与第二主设备进行仲裁或干扰。