公开(公告)号：US06509202B1

公开(公告)日：2003-01-21

申请号：US09875073

申请日：2001-06-05

申请人： Hyeon-Seag Kim

发明人： Hyeon-Seag Kim

IPC分类号： H01L2166

CPC分类号： G01R31/2648 ,  H01L21/28282 ,  H01L21/3144

摘要： A method and system for qualifying an oxide-nitride-oxide (ONO) layer including a first oxide layer, a nitride layer and a control oxide layer in a semiconductor device is disclosed. The method and system include determining the lifetime of the ONO layer using the activation energy of the ONO layer and the field acceleration factor of the ONO layer. The activation energy and field acceleration factor of the ONO layer are determined by testing a plurality of ONO layers, some of which have a particular nitride layer thickness and varying control oxide layer thicknesses and others which have a particular control oxide layer thicknesses and varying nitride layer thicknesses. The plurality of ONO layers is tested using a variety of applied voltages to obtain lifetimes for the plurality of ONO layers. Based on these lifetimes and voltages, the activation energy and field acceleration factor for the ONO layer can be obtained.

摘要翻译： 公开了一种用于限定半导体器件中包括第一氧化物层，氮化物层和控制氧化物层的氧化物 - 氧化物（ONO）层的方法和系统。 该方法和系统包括使用ONO层的活化能和ONO层的场加速因子确定ONO层的寿命。 通过测试多个ONO层来确定ONO层的激活能和场加速因子，其中一些ONO层具有特定的氮化物层厚度和改变的控制氧化物层厚度，而其它ONO层具有特定的控制氧化层厚度和改变的氮化物层 厚度 使用各种施加的电压来测试多个ONO层以获得多个ONO层的寿命。 基于这些寿命和电压，可以获得ONO层的活化能和场加速因子。

公开(公告)号：US06413826B2

公开(公告)日：2002-07-02

申请号：US09287976

申请日：1999-04-07

申请人： Hyeon-Seag Kim

发明人： Hyeon-Seag Kim

IPC分类号： H01L21336

CPC分类号： H01L21/823462 ,  H01L21/823481

摘要： Methods of manufacturing insulating materials and semiconductor devices incorporating films having high dielectric constants are disclosed, in which the high-dielectric constant material is deposited on a semiconductor surface that has been treated to prevent the formation of interfacial oxide between the semiconductor substrate and the high, dielectric constant material. The methods of this invention involve implantation of nitrogen ions through the sacrificial oxide layer, thereby forming a nitrided silicon substrate underneath the sacrificial oxide. The sacrificial oxide can then removed, and thereafter layers of high dielectric constant materials can be deposited on the nitrided silicon substrate without the formation of interfacial oxide. Manufacturing devices using the methods of this invention can result in the formation of an overall insulating film having a dielectric constant that more closely reflects the dielectric constant of the high-dielectric constant material. Therefore, the insulating films made using the methods of this invention can be made thinner than conventional insulating films, thus permitting the manufacture of semiconductor products having increasing device density and increasing efficiency, and decreasing manufacturing costs.

摘要翻译： 公开了制造具有高介电常数的膜的绝缘材料和半导体器件的制造方法，其中将高介电常数材料沉积在半导体表面上，该半导体表面已经被处理以防止半导体衬底和高介电常数之间形成界面氧化物， 介电常数材料。 本发明的方法涉及通过牺牲氧化物层注入氮离子，从而在牺牲氧化物下方形成氮化硅衬底。 然后可以去除牺牲氧化物，然后可以在氮化硅衬底上沉积高介电常数材料层，而不形成界面氧化物。 使用本发明的方法的制造装置可以形成具有更接近反映高介电常数材料的介电常数的介电常数的整体绝缘膜。 因此，使用本发明的方法制造的绝缘膜可以比常规绝缘膜更薄，从而允许制造具有增加的器件密度和提高效率以及降低制造成本的半导体产品。

公开(公告)号：US06297128B1

公开(公告)日：2001-10-02

申请号：US09240560

申请日：1999-01-29

申请人： Hyeon-Seag Kim ,  Sunil D. Mehta

发明人： Hyeon-Seag Kim ,  Sunil D. Mehta

IPC分类号： H01L2176

CPC分类号： H01L21/76224

摘要： This invention provides methods for reducing the mechanical stresses within dielectric layers filling the gaps in shallow trench isolation (STI) regions on semiconductor wafers. The methods include the sequential deposition of alternating layers of dielectric materials having tensile stress and compressive stress, respectively. The invention also provides methods for adjusting the residual stress in a dielectric film by controlling the relative thicknesses of the alternating layers of dielectric material to provide bilayers having minimal overall stress. Additionally, the invention provides semiconductor devices having the reduced stress dielectric materials within the shallow isolation trenches of the semiconductor wafer. The reduction in stress within and between trenches decreases defects in the shallow isolation materials and thereby decreases source-drain and trench—trench short circuiting. The improved electrical and mechanical properties of the shallow trench filling materials makes practical the manufacture of more reliable, smaller semiconductor devices.

摘要翻译： 本发明提供了减少填充半导体晶片上的浅沟槽隔离（STI）区域中的间隙的电介质层内的机械应力的方法。 这些方法包括分别具有拉伸应力和压缩应力的交替层的介电材料的顺序沉积。 本发明还提供了通过控制介电材料的交替层的相对厚度以提供具有最小总应力的双层来调节电介质膜中的残余应力的方法。 此外，本发明提供了在半导体晶片的浅隔离沟槽内具有减小的应力介电材料的半导体器件。 沟槽内和沟槽之间的应力减小降低了浅隔离材料的缺陷，从而减少了源极 - 漏极和沟槽沟槽短路。 浅沟槽填充材料的改进的电气和机械性能使得制造更可靠，更小的半导体器件成为可能。

公开(公告)号：US6133164A

公开(公告)日：2000-10-17

申请号：US256245

申请日：1999-02-23

申请人： Hyeon-Seag Kim

发明人： Hyeon-Seag Kim

IPC分类号： H01L21/8234

CPC分类号： H01L21/823462

摘要： The present invention is a method for fabricating a plurality of oxide regions having a plurality of thicknesses on a semiconductor wafer. The present invention includes a step of depositing a first masking layer on the semiconductor wafer, and the first masking layer defines at least one first region for oxide growth of a first thickness. The present invention also includes a step of implanting oxygen ions into the at least one first region such that the first thickness of oxide on the at least one first region is relatively thicker. The first masking layer is then removed from the semiconductor wafer. The present invention further includes a step of depositing a second masking layer on the semiconductor wafer, and the second masking layer defines at least one second region for oxide growth of a second thickness. The present invention also includes a step of implanting nitrogen ions into the at least one second region such that the second thickness of oxide on the at least one second region is relatively thinner. The second masking layer is then removed from the semiconductor wafer. The present invention further includes the step of growing oxide on the at least one first region to have the first thickness and on the at least one second region to have the second thickness with a thermal process for the semiconductor wafer. During the thermal process, at least one third region of oxide may be grown to have a third thickness which is thinner than the oxide on the at least one first region and that is thicker than the oxide on the at least one second region since the at least one third region has not been exposed to oxygen ion implantation nor to nitrogen ion implantation.

摘要翻译： 本发明是一种在半导体晶片上制造具有多个厚度的多个氧化物区域的方法。 本发明包括在半导体晶片上沉积第一掩模层的步骤，并且第一掩蔽层限定用于第一厚度的氧化物生长的至少一个第一区域。 本发明还包括将氧离子注入到至少一个第一区域中的步骤，使得至少一个第一区域上的第一厚度的氧化物相对较厚。 然后从半导体晶片去除第一掩模层。 本发明还包括在半导体晶片上沉积第二掩蔽层的步骤，并且第二掩蔽层限定用于第二厚度的氧化物生长的至少一个第二区域。 本发明还包括将氮离子注入到至少一个第二区域中的步骤，使得至少一个第二区域上的第二厚度的氧化物相对较薄。 然后从半导体晶片去除第二掩模层。 本发明还包括在所述至少一个第一区域上生长氧化物以具有第一厚度并且在至少一个第二区域上具有用于半导体晶片的热处理的第二厚度的步骤。 在热处理期间，可以生长至少一个第三区域的氧化物以具有比至少一个第一区域上的氧化物更薄的第三厚度，并且比第一区域上的氧化物厚，因为在 至少一个第三区域没有暴露于氧离子注入和氮离子注入。