公开(公告)号：US20070018693A1

公开(公告)日：2007-01-25

申请号：US11420098

申请日：2006-05-24

Applicant: Jinghong Chen

Inventor： Jinghong Chen

IPC: H03K19/094

CPC classification number: H03K19/09432

Abstract: A CML digital circuit includes a load coupled between a power supply node and at least one output node and a logic circuit component coupled to the output node. The logic circuit component has at least one data input node. The logic circuit component comprises a first circuit module and a second circuit module. A first tail current source is coupled to the first circuit module. A second tail current source is coupled to the second circuit module. A first switch is coupled between the power supply node and the first tail current source. A second switch is coupled between the power supply node and the second tail current source, wherein the first switch is triggered to deactivate the first circuit module when the second circuit module is operating and the second switch is triggered to deactivate the second circuit module when the first circuit module is operating.

Abstract translation: CML数字电路包括耦合在电源节点和至少一个输出节点之间的负载以及耦合到输出节点的逻辑电路组件。 逻辑电路组件具有至少一个数据输入节点。 逻辑电路部件包括第一电路模块和第二电路模块。 第一尾电流源耦合到第一电路模块。 第二尾电流源耦合到第二电路模块。 第一开关耦合在电源节点和第一尾电流源之间。 第二开关耦合在电源节点和第二尾电流源之间，其中第一开关被触发以在第二电路模块工作时停用第一电路模块，并且当第二开关被触发时停用第二电路模块 第一个电路模块正在运行。