公开(公告)号：US4370627A

公开(公告)日：1983-01-25

申请号：US135669

申请日：1980-03-31

申请人： Kenji Kaneko ,  Takahiro Okabe

发明人： Kenji Kaneko ,  Takahiro Okabe

IPC分类号： H01L27/02 ,  H03K3/283 ,  H03F3/195 ,  H03B5/36 ,  H03F3/18

CPC分类号： H03K3/283 ,  H01L27/0233

摘要： An oscillation circuit including an amplifier portion wherein the collector of a first switching transistor has a load connected thereto, means is provided for transmitting an output of the collector of the first switching transistor to the base thereof, means is provided for transmitting the output of the collector of the first switching transistor to the base of a second switching transistor, and the collector of the second switching transistor has a load connected thereto. A capacitive element is connected between the collector of the second switching transistor and the base of the first switching transistor of the amplifier portion so as to feedback an output of the second switching transistor to the first switching transistor to operate the circuit as an oscillator.

摘要翻译： 一种振荡电路，包括：放大器部分，其中第一开关晶体管的集电极具有与其连接的负载，提供用于将第一开关晶体管的集电极的输出传输到其基极的装置，用于传输第 第一开关晶体管的集电极到第二开关晶体管的基极，并且第二开关晶体管的集电极具有与其连接的负载。 电容元件连接在第二开关晶体管的集电极和放大器部分的第一开关晶体管的基极之间，以将第二开关晶体管的输出反馈到第一开关晶体管，以将该电路作为振荡器进行操作。

公开(公告)号：US4051389A

公开(公告)日：1977-09-27

申请号：US666418

申请日：1976-03-12

申请人： Kenji Kaneko ,  Takahiro Okabe

发明人： Kenji Kaneko ,  Takahiro Okabe

IPC分类号： G11C11/411 ,  H01L27/102 ,  H03K3/288 ,  H03K3/29

CPC分类号： H01L27/1025 ,  G11C11/4113 ,  H03K3/288

摘要： A flip-flop circuit comprises a pair of inversely operated first and second npn vertical transistors. The first npn transistor has dual collectors. Also provided are a pair of first and second pnp lateral transistors operated as loads and a pair of third and fourth pnp lateral transistors for triggering, each base of the first and second npn vertical transistors being connected to a collector of the second npn transistor and to one of the dual collectors of the first npn transistor, respectively. Each collector of the first and second pnp transistors is connected to said one of the dual collectors of the first npn transistor and to the collector of the second npn transistor, respectively. Each emitter of the first and second pnp transistors is connected to an electric source, each base of the first and second npn transistors is connected to each emitter of the third and fourth pnp transistors, respectively, and each base of the third and fourth pnp transistors is connected to said one of the dual collectors of the first npn transistor through a first resistor and to the collector of the second npn transistor through a second resistor. Each collector of the third and fourth pnp transistors is connected to an input terminal for trigger signals, an output terminal is connected to the other collector of the dual collectors of the first npn transistor, and each emitter of the first and second npn transistors and each base of said first and second pnp transistors is grounded.