QUANTUM DOT LIGHT-EMITTING DEVICES AND METHODS OF PREPARING THE SAME, DISPLAY SUBSTRATES, AND DISPLAY APPARATUSES

    公开(公告)号:US20240244861A1

    公开(公告)日:2024-07-18

    申请号:US17921545

    申请日:2021-10-28

    Inventor: Dong LI

    CPC classification number: H10K50/115 H10K85/653 H10K85/654

    Abstract: The present disclosure relates to a quantum dot light-emitting device and a method of preparing the same, a display substrate, and a display apparatus. The quantum dot light-emitting device includes a first electrode layer, a light-emitting layer, and a second electrode layer, the light-emitting layer being provided between the first electrode layer and the second electrode layer, and the light-emitting layer including quantum dots and electrolytes, where the quantum dots are provided between the electrolytes in a direction from the first electrode layer to the second electrode layer; and the electrolytes undergo an electrochemical reaction in the presence of an electric field to provide an equal number of electrons and holes. According to the embodiments of the present disclosure, the electrons and holes injected into the quantum dots can be balanced, which is conducive to improving imbalance of carriers injected into the quantum dot light-emitting device, and thus improving the light-emitting efficiency of the quantum dot light-emitting device.

    THIN FILM TRANSISTOR, DISPLAY PANEL AND DISPLAY DEVICE

    公开(公告)号:US20240120422A1

    公开(公告)日:2024-04-11

    申请号:US17637479

    申请日:2021-02-26

    Abstract: The present disclosure provides a thin film transistor, a display panel and a display device. The thin film transistor includes a semiconductor material layer, a first insulating layer and a gate layer. The semiconductor material layer is at a side of a base substrate, and includes a first channel portion, a first doped portion and a second channel portion sequentially connected. The first insulating layer is at a side of the semiconductor material layer facing away from the base substrate. The gate layer is at a side of the first insulating layer facing away from the semiconductor material layer, and includes a first gate portion and a second gate portion. An orthographic projection of the first gate portion on the base substrate coincides with an orthographic projection of the first channel portion on the base substrate, and the first gate portion is configured to receive a gate driving signal.

    DISPLAY PANEL, DISPLAY DEVICE, AND MANUFACTURING METHOD

    公开(公告)号:US20210265453A1

    公开(公告)日:2021-08-26

    申请号:US17256192

    申请日:2020-04-22

    Abstract: A display panel, a display apparatus, and a manufacturing method are disclosed. The display panel includes a base substrate having a first through hole; a conductive structure located on the base substrate and at least partially covering the first through hole; and a display structure including a first display structure, a control line, and a second display structure that are arranged in layers on a side of the base substrate where the conductive structure is located, wherein the first display structure has a second through hole, and the control line is electrically connected to the conductive structure by passing through the second through hole.

    ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY PANEL AND DISPLAY DEVICE

    公开(公告)号:US20210210560A1

    公开(公告)日:2021-07-08

    申请号:US16766905

    申请日:2019-10-18

    Abstract: The present disclosure discloses an array substrate with a display area, a manufacturing method thereof, a display panel, and a display device. The array substrate with the display area includes a base substrate, and a thin film transistor structure on a surface of the base substrate. The thin film transistor structure is in the display area, the thin film transistor structure includes at least a source-drain pattern and a planarization pattern. The source-drain pattern and the planarization pattern are on a side of the thin film transistor structure away from the base substrate. A surface of the planarization pattern away from the base substrate and a surface of the source-drain pattern away from the base substrate are substantially in a same plane, the planarization pattern has a first slot, and the source-drain pattern is accommodated in the first slot.

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