公开(公告)号：US08027651B2

公开(公告)日：2011-09-27

申请号：US12329034

申请日：2008-12-05

申请人： Darrell J. Stogner ,  Yadunandana N. Rao ,  Charles R. Ruelke ,  Chet A. Lampert

发明人： Darrell J. Stogner ,  Yadunandana N. Rao ,  Charles R. Ruelke ,  Chet A. Lampert

IPC分类号： H04B17/02

CPC分类号： H04B1/30 ,  H04L25/061

摘要： A method and apparatus for correcting direct current (DC) offset errors of a received signal in a direct conversion receiver (DCR) are provided. DC offset correction algorithms are incorporated into the DCR, each algorithm being optimized for a particular receive signal operating environment. The DC offset correction algorithms remove DC offset errors in baseband In-phase and Quadrature-phase signals received within the direct conversion receiver baseband signal path. Individual DC offset correction algorithms are selected for use as determined by a signal quality estimator component. A DC offset correction component of the direct conversion receiver determines an appropriate DC offset correction algorithm suited for a particular operating environment. A criterion for a signal quality estimate is set to control transitioning between DCOC algorithms. A dual threshold strategy may be adopted to transition between one DC offset correction algorithm and another DC offset correction algorithm to provide hysteresis.

摘要翻译： 提供一种用于校正直接转换接收机（DCR）中的接收信号的直流（DC）偏移误差的方法和装置。 DC偏移校正算法被并入到DCR中，每个算法针对特定的接收信号操作环境进行优化。 DC偏移校正算法消除了在直接转换接收机基带信号路径内接收的基带同相和正交相信号中的直流失调误差。 选择单个DC偏移校正算法以由信号质量估计器组件确定使用。 直接转换接收机的DC偏移校正分量确定适合于特定操作环境的适当DC偏移校正算法。 设置信号质量估计的标准来控制DCOC算法之间的转换。 可以采用双阈值策略来在一个DC偏移校正算法和另一个DC偏移校正算法之间转换以提供滞后。

公开(公告)号：US20080240312A1

公开(公告)日：2008-10-02

申请号：US11694697

申请日：2007-03-30

申请人： Charles R. Ruelke ,  William J. Rinderknecht

发明人： Charles R. Ruelke ,  William J. Rinderknecht

IPC分类号： H04L27/08

CPC分类号： H03G3/3068

摘要： A radio receiver (300) having a multi-state variable threshold automatic gain control (AGC) for fast channel scanning acquisition includes an amplifier (303) having an automatic gain control (AGC) for controlling the gain of a receiver analog signal. An analog-to-digital converter (ADC) (311) is used for converting the receiving analog signal to a digital signal while a digital signal processor (DSP) (325) operates to process the digital signal. A signal magnitude estimator (315) in an AGC controller (313) provides a signal strength estimate of the received signal. The AGC controller (313) then sets the receiver amplifier (303) for an open-loop AGC operational mode and sets a first threshold for triggering an interrupt service request (ISR). This ISR is provided the DSP (325) and the host processor (327) if a radio frequency (RF) signal is detected above a first threshold during a priority scan of a priority channel to minimize interruptions in audio during priority scan.

摘要翻译： 具有用于快速信道扫描获取的多状态可变阈值自动增益控制（AGC）的无线电接收机（300）包括具有用于控制接收机模拟信号的增益的自动增益控制（AGC）的放大器（303）。 当数字信号处理器（DSP）（325）操作以处理数字信号时，模数转换器（ADC）（311）用于将接收模拟信号转换为数字信号。 AGC控制器（313）中的信号幅度估计器（315）提供接收信号的信号强度估计。 然后，AGC控制器（313）将接收机放大器（303）设置为开环AGC操作模式，并设置触发中断服务请求（ISR）的第一阈值。 如果在优先级信道的优先扫描期间检测到高于第一阈值的射频（RF）信号，则在最优化扫描期间最小化音频中断，则该ISR被提供给DSP（325）和主机处理器（327）。

公开(公告)号：US07203476B2

公开(公告)日：2007-04-10

申请号：US10754654

申请日：2004-01-09

申请人： Charles R. Ruelke ,  Richard S. Young

发明人： Charles R. Ruelke ,  Richard S. Young

IPC分类号： H04B1/26

CPC分类号： H04B1/30 ,  H03D3/008

摘要： An adaptive dc compensation technique (100) eliminates dc error for both digital and constant envelope modulation protocols (108). For analog modulation, a dc averaging technique utilizes piece-wise continuous dc averaging (110) that calculates discrete dc error values over a variable number of samples (112) and updates the dc compensation value as a fixed value for a specified sample length (114). The piece-wise “update-and-hold” technique (110) results in a pseudo high pass filter response with an equivalent corner. For digital modulation, a continuous high pass filter section of the receiver is enabled (120).

摘要翻译： 自适应直流补偿技术（100）消除数字和恒定包络调制协议（108）的直流误差。 对于模拟调制，直流平均技术使用分段连续直流平均（110），其在可变数量的样本（112）上计算离散直流误差值，并将直流补偿值更新为指定样本长度的固定值（114 ）。 分段式“更新和保持”技术（110）导致具有等效角的伪高通滤波器响应。 对于数字调制，使能接收器的连续高通滤波器部分（120）。

公开(公告)号：US06459889B1

公开(公告)日：2002-10-01

申请号：US09515288

申请日：2000-02-29

申请人： Charles R. Ruelke

发明人： Charles R. Ruelke

IPC分类号： H04B110

CPC分类号： H04B1/30

摘要： A receiver direct current offset correction loop (DCOCL) circuit digitizes the baseband analog control voltage (148) using an Analog-to-Digital Converter (ADC) block 160, which is then processed at control block (162) to drive compensation circuitry 164 in a classic feedback configuration. The DCOCL is augmented by an independent automatic gain control (AGC) circuit that utilizes the same control signal (148). The AGC circuit includes a multiplicity of adjustable gain stages (114, 118, 158) with threshold and characteristic response that is controlled by AGC control block (122). Both the AGC and DCOCL circuits are dynamically configured for optimum complimentary operation via the microprocessor (236) depending on the receiver's operating environment and protocol requirements. Subsequent direct current (DC) voltage drift is detected by the digital signal processor (DSP) block (230) which in turn flags the microprocessor to reinitiate the correction sequence when needed. Subsequent to the microprocessor controlled hardware correction sequence, the DSP digitally equalizes any remaining offset errors in the recovered data through a multiplicity of compensation algorithms optimized to specific operating environments. This provides for optimum correction of the baseband DC offsets with minimal degradation of receiver performance.

摘要翻译： 接收机直流偏移校正回路（DCOCL）电路使用模数转换器（ADC）块160对基带模拟控制电压（148）进行数字化，然后在控制块（162）处理该模拟控制电压以驱动补偿电路164 一个经典的反馈配置。 DCOCL由利用相同控制信号（148）的独立自动增益控制（AGC）电路来增强。 AGC电路包括由AGC控制块（122）控制的具有阈值和特性响应的多个可调增益级（114,118,158）。 动态地配置AGC和DCOCL电路，以根据接收机的操作环境和协议要求通过微处理器（236）实现最佳的互补操作。 随后的直流（DC）电压漂移由数字信号处理器（DSP）块（230）检测，数字信号处理器（DSP）块进而标记微处理器以在需要时重新启动校正序列。 在微处理器控制的硬件校正序列之后，DSP通过针对特定操作环境优化的多种补偿算法数字地均衡恢复数据中的任何剩余偏移误差。 这提供了基带DC偏移的最佳校正，同时接收机性能的降低最小。

公开(公告)号：US5574413A

公开(公告)日：1996-11-12

申请号：US397458

申请日：1995-03-02

申请人： Charles R. Ruelke

发明人： Charles R. Ruelke

IPC分类号： H03H7/12

CPC分类号： H03H7/12 ,  H03H7/1766 ,  H03H7/1775

摘要： A tunable filter (100) includes first and second resonant structures (140, 145) coupled by a capacitive coupler (120). The capacitive coupler (120) includes two tunable elements (121, 126) coupled by a capacitive circuit formed at least in part by a capacitive pi-network (130).

摘要翻译： 可调滤波器（100）包括由电容耦合器（120）耦合的第一和第二谐振结构（140,145）。 电容耦合器（120）包括通过至少部分由电容式π网络（130）形成的电容电路耦合的两个可调元件（121,126）。