公开(公告)号：US20190317978A1

公开(公告)日：2019-10-17

申请号：US16433027

申请日：2019-06-06

Applicant: D-WAVE SYSTEMS INC.

Inventor： Mohammad H. Amin ,  Evgeny A. Andriyash

IPC: G06F17/17 ,  G06N10/00 ,  G06F17/13 ,  G06F17/18 ,  G06N7/00 ,  G06F9/30 ,  H04L9/08 ,  G06F5/01

Abstract: The systems, devices, articles, and methods generally relate to sampling from an available probability distribution. The samples maybe used to create a desirable probability distribution, for instance for use in computing values used in computational techniques including: Importance Sampling and Markov chain Monte Carlo systems. An analog processor may operate as a sample generator, for example by: programming the analog processor with a configuration of the number of programmable parameters for the analog processor, which corresponds to a probability distribution over qubits of the analog processor, evolving the analog processor with a fast ramp operation, and reading out states for the qubits. The state for the qubits may be post processes and/or used to calculate importance weights.

公开(公告)号：US20190266510A1

公开(公告)日：2019-08-29

申请号：US16308314

申请日：2017-06-07

Applicant: Sheir YARKONI ,  D-WAVE SYSTEMS INC.

Inventor： Sheir Yarkoni ,  Trevor Michael Lanting ,  Kelly T. R. Boothby ,  Andrew Douglas King ,  Evgeny A. Andriyash ,  Mohammad H. Amin

IPC: G06N10/00 ,  G06N7/08 ,  B82Y10/00

Abstract: A hybrid computer for generating samples employs a digital computer operable to perform post-processing. An analog computer may be communicatively coupled to the digital computer. The analog computer may be operable to return one or more samples corresponding to low-energy configurations of a Hamiltonian. Methods of generating samples from a quantum Boltzmann distribution to train a Quantum Boltzmann Machine, and from a classical Boltzmann distribution to train a Restricted Boltzmann Machine, are also taught. Computational systems and methods permit processing problems having size and/or connectivity greater than, and/or at least not fully provided by, a working graph of an analog processor. The approach may include determining preparatory biases toward a first classical spin configuration, evolving the analog processor in a first direction; evolving the analog processor in a second direction and evolving the analog processor in the first direction until the analog processor reaches a second classical spin configuration.