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    SYSTEMS AND METHODS FOR QUANTUM COMPUTATION
    2.
    发明申请
    SYSTEMS AND METHODS FOR QUANTUM COMPUTATION 审中-公开

    公开(公告)号：US20200320424A1

    公开(公告)日：2020-10-08

    申请号：US16858108

    申请日：2020-04-24

    Applicant: D-WAVE SYSTEMS INC.

    Inventor： Sheir Yarkoni ,  Trevor Michael Lanting ,  Kelly T. R. Boothby ,  Andrew Douglas King ,  Evgeny A. Andriyash ,  Mohammad H. Amin

    IPC: G06N10/00 ,  B82Y10/00 ,  G06N7/08 ,  G06N3/04

    Abstract: A computational method via a hybrid processor comprising an analog processor and a digital processor includes determining a first classical spin configuration via the digital processor, determining preparatory biases toward the first classical spin configuration, programming an Ising problem and the preparatory biases in the analog processor via the digital processor, evolving the analog processor in a first direction, latching the state of the analog processor for a first dwell time, programming the analog processor to remove the preparatory biases via the digital processor, determining a tunneling energy via the digital processor, determining a second dwell time via the digital processor, evolving the analog processor in a second direction until the analog processor reaches the tunneling energy, and evolving the analog processor in the first direction until the analog processor reaches a second classical spin configuration.

    TOPOLOGICALLY PROTECTED QUBITS, PROCESSORS WITH TOPOLOGICALLY PROTECTED QUBITS, AND METHODS FOR USE OF TOPOLOGICALLY PROTECTED QUBITS
    4.
    发明公开
    TOPOLOGICALLY PROTECTED QUBITS, PROCESSORS WITH TOPOLOGICALLY PROTECTED QUBITS, AND METHODS FOR USE OF TOPOLOGICALLY PROTECTED QUBITS 审中-公开

    公开(公告)号：US20230370069A1

    公开(公告)日：2023-11-16

    申请号：US17883874

    申请日：2022-08-09

    Applicant: D-WAVE SYSTEMS INC.

    Inventor： Mohammad H. Amin ,  Richard G. Harris

    IPC: H03K19/195 ,  G06N10/40

    CPC classification number: H03K19/195 ,  G06N10/40

    Abstract: A logical qubit, a quantum processor, and a method of performing an operation on the logical qubit are discussed. The logical qubit includes first and second tunable couplers and a plurality of fixed couplers, with at least one fixed coupler providing four physical qubit interaction. The first and second tunable couplers and the fixed couplers enforce even parity in any connected qubits. The logical qubit has a plurality of physical qubits with qubits connected to the first tunable coupler and a first fixed coupler, qubits connected to the second tunable coupler and a second fixed coupler, and qubits connected between the first fixed coupler and the second fixed coupler. Each fixed coupler is connected to at least two physical qubits and at least two paths connect the first tunable coupler and the second tunable coupler, with one path communicating with a microwave line.

    Systems and methods for degeneracy mitigation in a quantum processor
    5.
    发明授权
    Systems and methods for degeneracy mitigation in a quantum processor 有权

    公开(公告)号：US11681940B2

    公开(公告)日：2023-06-20

    申请号：US17379172

    申请日：2021-07-19

    Applicant: D-WAVE SYSTEMS INC.

    Inventor： Andrew Douglas King ,  Alexandre Fréchette ,  Evgeny A. Andriyash ,  Trevor Michael Lanting ,  Emile M. Hoskinson ,  Mohammad H. Amin

    IPC: G06N10/00 ,  G06F15/163

    CPC classification number: G06N10/00 ,  G06F15/163

    Abstract: Degeneracy in analog processor (e.g., quantum processor) operation is mitigated via use of floppy qubits or domains of floppy qubits (i.e., qubit(s) for which the state can be flipped with no change in energy), which can significantly boost hardware performance on certain problems, as well as improve hardware performance for more general problem sets. Samples are drawn from an analog processor, and devices comprising the analog processor evaluated for floppiness. A normalized floppiness metric is calculated, and an offset added to advance the device in annealing. Degeneracy in a hybrid computing system that comprises a quantum processor is mitigated by determining a magnetic susceptibility of a qubit, and tuning a tunneling rate for the qubit based on a tunneling rate offset determined based on the magnetic susceptibility. Quantum annealing evolution is controlled by causing the evolution to pause for a determined pause duration.

    Re-equilibrated quantum sampling
    6.
    发明授权
    Re-equilibrated quantum sampling 有权

    公开(公告)号：US10346508B2

    公开(公告)日：2019-07-09

    申请号：US15870411

    申请日：2018-01-12

    Applicant: D-Wave Systems Inc.

    Inventor： Mohammad H. Amin ,  Evgeny A. Andriyash

    IPC: G06F17/17 ,  G06F17/18 ,  G06F9/30 ,  G06F17/13 ,  G06F5/01 ,  G06N10/00 ,  G06N7/00 ,  H04L9/08

    Abstract: The systems, devices, articles, and methods generally relate to sampling from an available probability distribution. The samples maybe used to create a desirable probability distribution, for instance for use in computing values used in computational techniques including: Importance Sampling and Markov chain Monte Carlo systems. An analog processor may operate as a sample generator, for example by: programming the analog processor with a configuration of the number of programmable parameters for the analog processor, which corresponds to a probability distribution over qubits of the analog processor, evolving the analog processor with a fast ramp operation, and reading out states for the qubits. The state for the qubits may be post processes and/or used to calculate importance weights.

    UNIVERSAL ADIABATIC QUANTUM COMPUTING WITH SUPERCONDUCTING QUBITS
    7.
    发明申请
    UNIVERSAL ADIABATIC QUANTUM COMPUTING WITH SUPERCONDUCTING QUBITS 审中-公开

    公开(公告)号：US20180314970A1

    公开(公告)日：2018-11-01

    申请号：US16029040

    申请日：2018-07-06

    Applicant: D-Wave Systems Inc.

    Inventor： Richard G. Harris ,  Mohammad H. Amin ,  Anatoly Smirnov

    IPC: G06N99/00 ,  H03K19/195

    CPC classification number: G06N99/002 ,  G11C11/44 ,  H03K3/38 ,  H03K19/1952

    Abstract: A quantum processor is operable as a universal adiabatic quantum computing system. The quantum processor includes physical qubits, with at least a first and second communicative coupling available between pairs of qubits via an in-situ tunable superconducting capacitive coupler and an in-situ tunable superconducting inductive coupler, respectively. Tunable couplers provide diagonal and off-diagonal coupling. Compound Josephson junctions (CJJs) of the tunable couplers are responsive to a flux bias to tune a sign and magnitude of a sum of a capacitance of a fixed capacitor and a tunable capacitance which is mediated across a pair of coupling capacitors. The qubits may be hybrid qubits, operable in a flux regime or a charge regime. Qubits may include a pair of CJJs that interrupt a loop of material and which are separated by an island of superconducting material which is voltage biased with respect to a qubit body.

    SYSTEMS AND METHODS FOR RANDOM NUMBER GENERATION
    8.
    发明公开
    SYSTEMS AND METHODS FOR RANDOM NUMBER GENERATION 审中-公开

    公开(公告)号：US20240168720A1

    公开(公告)日：2024-05-23

    申请号：US18113735

    申请日：2023-02-24

    Applicant: D-WAVE SYSTEMS INC.

    Inventor： Mohammad H. Amin

    IPC: G06F7/58 ,  G06N10/40 ,  H04L9/08

    CPC classification number: G06F7/582 ,  G06N10/40 ,  H04L9/0852

    Abstract: Systems and methods for random number generation are discussed. A first processor is in communication with a quantum processor, the quantum processor having an array of superconducting qubits. The first processor instructs the quantum processor to selectively communicatively couple the superconducting qubits to embed a quantum system having a highly entangled nontrivial ground state. The highly entangled nontrivial ground state comprising a uniform distribution of classical ground states. One or more distortions are introduced to the uniform distribution by one or more random variations based on an input value. The quantum processor evolves over the embedded quantum system. A set of one or more random numbers is received from the quantum processor.

    SYSTEMS AND METHODS FOR FABRICATION OF SUPERCONDUCTING INTEGRATED CIRCUITS WITH IMPROVED COHERENCE
    9.
    发明公开
    SYSTEMS AND METHODS FOR FABRICATION OF SUPERCONDUCTING INTEGRATED CIRCUITS WITH IMPROVED COHERENCE 审中-公开

    公开(公告)号：US20240138268A1

    公开(公告)日：2024-04-25

    申请号：US18277688

    申请日：2022-02-17

    Applicant: D-WAVE SYSTEMS INC.

    Inventor： Colin C. Enderud ,  Mohammad H. Amin ,  Loren J. Swenson

    IPC: H10N60/01 ,  H01L23/522 ,  H01L23/532 ,  H01L25/18 ,  H10N60/12 ,  H10N60/80 ,  H10N69/00

    CPC classification number: H10N60/0912 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/53285 ,  H01L25/18 ,  H10N60/12 ,  H10N60/805 ,  H10N69/00

    Abstract: A method of fabrication of a superconducting device includes forming a first portion of the superconducting device on a first chip, a second portion of the superconducting device on a second chip, and bonding the first chip to the second chip, arranged in a flip-chip configuration. The first portion of the superconducting device on the first chip includes a dissipative portion of the superconducting device. A multi-layer superconducting integrated circuit is implemented so that noise-susceptible superconducting devices are positioned in wiring layers formed from a low-noise superconductive material and that underlie wiring layers that are formed from a different superconductive material. A superconducting integrated circuit has a first stack with a first superconducting wiring layer formed from a first high kinetic inductance material and a second superconducting wiring layer communicatively coupled to the first superconducting wiring layer to form a first control circuit, a second stack comprising a third superconducting wiring layer formed from a second high kinetic inductance material and a fourth superconducting wiring layer communicatively coupled the third superconducting wiring layer to form a second control circuit. The superconducting integrated circuit also has a third stack with a controllable device, and at least one of the first control circuit and the second control circuit is communicatively coupled to the controllable device.

    SYSTEMS AND METHODS FOR IMPROVING THE PERFORMANCE OF NON-STOQUASTIC QUANTUM DEVICES
    10.
    发明申请
    SYSTEMS AND METHODS FOR IMPROVING THE PERFORMANCE OF NON-STOQUASTIC QUANTUM DEVICES 有权

    公开(公告)号：US20220215282A1

    公开(公告)日：2022-07-07

    申请号：US17602097

    申请日：2020-04-09

    Applicant: D-WAVE SYSTEMS INC.

    Inventor： Mohammad H. Amin

    IPC: G06N10/40 ,  G06N10/20

    Abstract: A technique for improving the performance of non-stoquastic quantum processors is provided. Clusters of qubits with correlated behavior are identified in a problem for processing by the quantum processor. Couplings between qubits in a common cluster are modified according to a transformation (for example, a gauge transformation) so that they evolve slower and thus their dynamics freeze out later (for example, by flipping anti-ferromagnetic couplings to ferromagnetic couplings). Couplings between qubits that do not belong to the common cluster may be flipped the other way (for example, from ferromagnetic couplings to anti-ferromagnetic couplings) to accelerate their dynamics. The quantum processor is evolved and the results are modified according to an inverse transformation.

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