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1.发明授权公开(公告)号：US11797874B2
公开(公告)日：2023-10-24
申请号：US17387654
申请日：2021-07-28
申请人： D-WAVE SYSTEMS INC.
发明人： Paul I. Bunyk , James King , Murray C. Thom , Mohammad H. Amin , Anatoly Smirnov , Sheir Yarkoni , Trevor M. Lanting , Andrew D. King , Kelly T. R. Boothby
CPC分类号： G06N10/00 , G06F11/0736 , G06F11/0751 , G06F11/0793
摘要： The systems, devices, articles, and methods described herein generally relate to analog computers, for example quantum processors comprising qubits, couplers, and, or cavities. Analog computers, for example quantum processor based computers, are the subject of various sources of error which can hinder operation, potentially reducing computational accuracy and speed. Sources of error can be broadly characterized, for example as i) a background susceptibility do to inherently characteristics of the circuitry design, ii) as an h/J ratio imbalance, iii) bit flip errors, iv) fidelity, and v) Anderson localization, and various combinations of the aforesaid.
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公开(公告)号：US20200320424A1
公开(公告)日：2020-10-08
申请号：US16858108
申请日：2020-04-24
申请人： D-WAVE SYSTEMS INC.
发明人： Sheir Yarkoni , Trevor Michael Lanting , Kelly T. R. Boothby , Andrew Douglas King , Evgeny A. Andriyash , Mohammad H. Amin
摘要： A computational method via a hybrid processor comprising an analog processor and a digital processor includes determining a first classical spin configuration via the digital processor, determining preparatory biases toward the first classical spin configuration, programming an Ising problem and the preparatory biases in the analog processor via the digital processor, evolving the analog processor in a first direction, latching the state of the analog processor for a first dwell time, programming the analog processor to remove the preparatory biases via the digital processor, determining a tunneling energy via the digital processor, determining a second dwell time via the digital processor, evolving the analog processor in a second direction until the analog processor reaches the tunneling energy, and evolving the analog processor in the first direction until the analog processor reaches a second classical spin configuration.
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公开(公告)号：US20240256930A1
公开(公告)日：2024-08-01
申请号：US18514482
申请日：2023-11-20
申请人： D-WAVE SYSTEMS INC.
发明人： Sheir Yarkoni , Trevor Michael Lanting , Kelly T. R. Boothby , Andrew Douglas King , Evgeny A. Andriyash , Mohammad H. Amin
摘要： A computational method via a hybrid processor comprising an analog processor and a digital processor includes determining a first classical spin configuration via the digital processor, determining preparatory biases toward the first classical spin configuration, programming an Ising problem and the preparatory biases in the analog processor via the digital processor, evolving the analog processor in a first direction, latching the state of the analog processor for a first dwell time, programming the analog processor to remove the preparatory biases via the digital processor, determining a tunneling energy via the digital processor, determining a second dwell time via the digital processor, evolving the analog processor in a second direction until the analog processor reaches the tunneling energy, and evolving the analog processor in the first direction until the analog processor reaches a second classical spin configuration.
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公开(公告)号：US20230370069A1
公开(公告)日：2023-11-16
申请号：US17883874
申请日：2022-08-09
申请人： D-WAVE SYSTEMS INC.
IPC分类号： H03K19/195 , G06N10/40
CPC分类号： H03K19/195 , G06N10/40
摘要： A logical qubit, a quantum processor, and a method of performing an operation on the logical qubit are discussed. The logical qubit includes first and second tunable couplers and a plurality of fixed couplers, with at least one fixed coupler providing four physical qubit interaction. The first and second tunable couplers and the fixed couplers enforce even parity in any connected qubits. The logical qubit has a plurality of physical qubits with qubits connected to the first tunable coupler and a first fixed coupler, qubits connected to the second tunable coupler and a second fixed coupler, and qubits connected between the first fixed coupler and the second fixed coupler. Each fixed coupler is connected to at least two physical qubits and at least two paths connect the first tunable coupler and the second tunable coupler, with one path communicating with a microwave line.
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公开(公告)号：US11681940B2
公开(公告)日：2023-06-20
申请号：US17379172
申请日：2021-07-19
申请人： D-WAVE SYSTEMS INC.
发明人： Andrew Douglas King , Alexandre Fréchette , Evgeny A. Andriyash , Trevor Michael Lanting , Emile M. Hoskinson , Mohammad H. Amin
IPC分类号： G06N10/00 , G06F15/163
CPC分类号： G06N10/00 , G06F15/163
摘要： Degeneracy in analog processor (e.g., quantum processor) operation is mitigated via use of floppy qubits or domains of floppy qubits (i.e., qubit(s) for which the state can be flipped with no change in energy), which can significantly boost hardware performance on certain problems, as well as improve hardware performance for more general problem sets. Samples are drawn from an analog processor, and devices comprising the analog processor evaluated for floppiness. A normalized floppiness metric is calculated, and an offset added to advance the device in annealing. Degeneracy in a hybrid computing system that comprises a quantum processor is mitigated by determining a magnetic susceptibility of a qubit, and tuning a tunneling rate for the qubit based on a tunneling rate offset determined based on the magnetic susceptibility. Quantum annealing evolution is controlled by causing the evolution to pause for a determined pause duration.
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公开(公告)号：US10346508B2
公开(公告)日：2019-07-09
申请号：US15870411
申请日：2018-01-12
申请人： D-Wave Systems Inc.
摘要： The systems, devices, articles, and methods generally relate to sampling from an available probability distribution. The samples maybe used to create a desirable probability distribution, for instance for use in computing values used in computational techniques including: Importance Sampling and Markov chain Monte Carlo systems. An analog processor may operate as a sample generator, for example by: programming the analog processor with a configuration of the number of programmable parameters for the analog processor, which corresponds to a probability distribution over qubits of the analog processor, evolving the analog processor with a fast ramp operation, and reading out states for the qubits. The state for the qubits may be post processes and/or used to calculate importance weights.
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公开(公告)号：US20180314970A1
公开(公告)日：2018-11-01
申请号：US16029040
申请日：2018-07-06
申请人： D-Wave Systems Inc.
IPC分类号： G06N99/00 , H03K19/195
CPC分类号： G06N99/002 , G11C11/44 , H03K3/38 , H03K19/1952
摘要： A quantum processor is operable as a universal adiabatic quantum computing system. The quantum processor includes physical qubits, with at least a first and second communicative coupling available between pairs of qubits via an in-situ tunable superconducting capacitive coupler and an in-situ tunable superconducting inductive coupler, respectively. Tunable couplers provide diagonal and off-diagonal coupling. Compound Josephson junctions (CJJs) of the tunable couplers are responsive to a flux bias to tune a sign and magnitude of a sum of a capacitance of a fixed capacitor and a tunable capacitance which is mediated across a pair of coupling capacitors. The qubits may be hybrid qubits, operable in a flux regime or a charge regime. Qubits may include a pair of CJJs that interrupt a loop of material and which are separated by an island of superconducting material which is voltage biased with respect to a qubit body.
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8.发明公开公开(公告)号：US20240237555A9
公开(公告)日：2024-07-11
申请号：US18277688
申请日：2022-02-17
申请人： D-WAVE SYSTEMS INC.
IPC分类号： H10N60/01 , H01L23/522 , H01L23/532 , H01L25/18 , H10N60/12 , H10N60/80 , H10N69/00
CPC分类号： H10N60/0912 , H01L23/5223 , H01L23/5227 , H01L23/53285 , H01L25/18 , H10N60/12 , H10N60/805 , H10N69/00
摘要： A method of fabrication of a superconducting device includes forming a first portion of the superconducting device on a first chip, a second portion of the superconducting device on a second chip, and bonding the first chip to the second chip, arranged in a flip-chip configuration. The first portion of the superconducting device on the first chip includes a dissipative portion of the superconducting device. A multi-layer superconducting integrated circuit is implemented so that noise-susceptible superconducting devices are positioned in wiring layers formed from a low-noise superconductive material and that underlie wiring layers that are formed from a different superconductive material. A superconducting integrated circuit has a first stack with a first superconducting wiring layer formed from a first high kinetic inductance material and a second superconducting wiring layer communicatively coupled to the first superconducting wiring layer to form a first control circuit, a second stack comprising a third superconducting wiring layer formed from a second high kinetic inductance material and a fourth superconducting wiring layer communicatively coupled the third superconducting wiring layer to form a second control circuit. The superconducting integrated circuit also has a third stack with a controllable device, and at least one of the first control circuit and the second control circuit is communicatively coupled to the controllable device.
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公开(公告)号：US11593695B2
公开(公告)日：2023-02-28
申请号：US16830650
申请日：2020-03-26
申请人： D-WAVE SYSTEMS INC.
发明人： William W. Bernoudy , Mohammad H. Amin , James A. King , Jeremy P. Hilton , Richard G. Harris , Andrew J. Berkley , Kelly T. R. Boothby
摘要： A hybrid computing system for solving a computational problem includes a digital processor, a quantum processor having qubits and coupling devices that together define a working graph of the quantum processor, and at least one nontransitory processor-readable medium communicatively coupleable to the digital processor which stores at least one of processor-executable instructions or data. The digital processor receives a computational problem, and programs the quantum processor with a first set of bias fields and a first set of coupling strengths. The quantum processor generates samples as potential solutions to an approximation of the problem. The digital processor updates the approximation by determining a second set of bias fields based at least in part on the first set of bias fields and a first set of mean fields that are based at least in part on the first set of samples and coupling strengths of one or more virtual coupling devices.
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公开(公告)号：US11494683B2
公开(公告)日：2022-11-08
申请号：US16955526
申请日：2018-12-19
申请人： D-Wave Systems Inc.
发明人： Mohammad H. Amin , Paul I. Bunyk , Trevor M. Lanting , Chunqing Deng , Anatoly Smirnov , Kelly T. R. Boothby , Emile M. Hoskinson , Christopher B. Rich
摘要： Josephson junctions (JJ) may replace primary inductance of transformers to realize galvanic coupling between qubits, advantageously reducing size. A long-range symmetric coupler may include a compound JJ (CJJ) positioned at least approximately at a half-way point along the coupler to advantageously provide a higher energy of a first excited state than that of an asymmetric long-range coupler. Quantum processors may include qubits and couplers with a non-stoquastic Hamiltonian to enhance multi-qubit tunneling during annealing. Qubits may include additional shunt capacitances, e.g., to increase overall quality of a total capacitance and improve quantum coherence. A sign and/or magnitude of an effective tunneling amplitude Δeff of a qubit characterized by a double-well potential energy may advantageously be tuned. Sign-tunable electrostatic coupling of qubits may be implemented, e.g., via resonators, and LC-circuits. YY couplings may be incorporated into a quantum anneaier (e.g., quantum processor).
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