公开(公告)号：US06999433B2

公开(公告)日：2006-02-14

申请号：US10272881

申请日：2002-10-17

Applicant: David Baum

Inventor： David Baum

IPC: H04Q7/00

CPC classification number: H04L12/6418 ,  H04L2012/6427 ,  H04L2012/6475 ,  H04L2012/6478 ,  H04M11/062

Abstract: HPNA MxU network for an MxU, the MxU including a plurality of HPNA LANs, each of the HPNA LANs operating according to a synchronous communication specification. Each of the HPNA LANs includes a plurality of nodes, one of the nodes within each HPNA LAN being a gateway node, a selected one of the nodes within each HPNA LAN being defined a LAN-master node and each HPNA LAN is coupled with a WAN via the respective gateway node. The LAN-master nodes allow the gateway nodes to transmit within a selected HPNA LAN downstream signals during at least one time slot, and the LAN-master nodes allow the nodes other than the gateway nodes to transmit upstream signals within a selected HPNA LAN to the respective gateway or transmit HN signals within a selected HPNA LAN, between nodes other than the respective gateway nodes during at least another timeslot.

Abstract translation: 用于MxU的HPNA MxU网络，MxU包括多个HPNA LAN，每个HPNA LAN根据同步通信规范进行操作。 每个HPNA LAN包括多个节点，每个HPNA LAN中的一个节点是网关节点，每个HPNA LAN中的所选节点之一被定义为LAN主节点，并且每个HPNA LAN与WAN相连 通过相应的网关节点。 LAN主节点允许网关节点在至少一个时隙内在选定的HPNA LAN下行信号内传输，并且LAN主节点允许除了网关节点之外的节点将选定的HPNA LAN内的上行信号传输到 在至少另一个时隙内，在相应网关节点之外的节点之间，在所选择的HPNA LAN内相应的网关或发送HN信号。

公开(公告)号：US20050051853A1

公开(公告)日：2005-03-10

申请号：US10656451

申请日：2003-09-05

Applicant: David Baum ,  Rodney Burt

Inventor： David Baum ,  Rodney Burt

IPC: H01L27/02 ,  H03F3/30 ,  H01L29/745

CPC classification number: H03F3/3061 ,  H01L27/0207 ,  H03F2200/366

Abstract: A complementary output stage in integrated circuit includes a P-channel transistor (MP1) the segmented into a first group of sections (MP1-1,2 . . . 12) and an N-channel transistor (MN1) segmented into a second group of sections (MN1-1,2 . . . 12). The sections of the first group are disposed in a plurality of N-type well regions (35), respectively, and the sections of the second group are disposed in a plurality of P-type well regions (36), respectively. The sections of the first group are alternately located with respect to the sections of the second group so as to form an interdigitated output stage area of the integrated circuit including the P-channel transistor (MP1) and the N-channel transistor (MN1) so that the higher amount of heat normally generated in the N-channel transistor is dissipated over the entire interdigitated output stage area and reduces peak temperatures in the N-channel transistor.

Abstract translation: 集成电路中的互补输出级包括被分段成第一组部分（MP1-1,2.12）的P沟道晶体管（MP1）和分割成第二组 （MN1-1,2 .12）。 第一组的部分分别设置在多个N型阱区（35）中，第二组的部分分别设置在多个P型阱区域（36）中。 第一组的部分相对于第二组的部分交替地定位，以便形成包括P沟道晶体管（MP1）和N沟道晶体管（MN1）的集成电路的交错输出级区域，从而 通常在N沟道晶体管中产生的较高的热量在整个交叉输出级区域上消散，并降低N沟道晶体管中的峰值温度。