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31.发明授权Bipolar transistor with raised extrinsic self-aligned base using selective epitaxial growth for BiCMOS integration 有权双极晶体管具有凸起的外部自对准基极，使用BiCMOS集成的选择性外延生长公开(公告)号：US07892910B2
公开(公告)日：2011-02-22
申请号：US11680163
申请日：2007-02-28
IPC分类号： H01L21/8238
CPC分类号： H01L29/7302 , H01L21/8249 , H01L27/0623 , H01L29/1004 , H01L29/66287
摘要： High performance bipolar transistors with raised extrinsic self-aligned base are integrated into a BiCMOS structure containing CMOS devices. By forming pad layers and raising the height of an intrinsic base layer relative to the source and drain of preexisting CMOS devices and by forming an extrinsic base through selective epitaxy, the effect of topographical variations is minimized during a lithographic patterning of the extrinsic base. Also, by not employing any chemical mechanical planarization process during the fabrication of the bipolar structures, complexity of process integration is reduced. Internal spacers or external spacers may be formed to isolate the base from the emitter. The pad layers, the intrinsic base layer, and the extrinsic base layer form a mesa structure with coincident outer sidewall surfaces.
摘要翻译： 具有凸起的外部自对准基极的高性能双极晶体管集成到包含CMOS器件的BiCMOS结构中。 通过形成焊盘层并相对于先前存在的CMOS器件的源极和漏极提高本征基极层的高度，并且通过选择性外延形成外部基极，在外部基极的光刻图案化期间，拓扑变化的影响被最小化。 而且，通过在双极结构的制造期间不采用任何化学机械平面化工艺，工艺集成的复杂性降低。 可以形成内部间隔物或外部隔离物以将基底与发射器隔离。 垫层，本征基层和非本征基层形成具有重合的外侧壁表面的台面结构。
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32.发明申请BIPOLAR TRANSISTOR WITH RAISED EXTRINSIC SELF-ALIGNED BASE USING SELECTIVE EPITAXIAL GROWTH FOR BICMOS INTEGRATION 有权使用选择性外延生长用于BICMOS整合的具有增强的自对准基底的双极晶体管公开(公告)号：US20080203490A1
公开(公告)日：2008-08-28
申请号：US11680163
申请日：2007-02-28
IPC分类号： H01L29/73 , H01L21/8238
CPC分类号： H01L29/7302 , H01L21/8249 , H01L27/0623 , H01L29/1004 , H01L29/66287
摘要： High performance bipolar transistors with raised extrinsic self-aligned base are integrated into a BiCMOS structure containing CMOS devices. By forming pad layers and raising the height of an intrinsic base layer relative to the source and drain of preexisting CMOS devices and by forming an extrinsic base through selective epitaxy, the effect of topographical variations is minimized during a lithographic patterning of the extrinsic base. Also, by not employing any chemical mechanical planarization process during the fabrication of the bipolar structures, complexity of process integration is reduced. Internal spacers or external spacers may be formed to isolate the base from the emitter. The pad layers, the intrinsic base layer, and the extrinsic base layer form a mesa structure with coincident outer sidewall surfaces.
摘要翻译： 具有凸起的外部自对准基极的高性能双极晶体管集成到包含CMOS器件的BiCMOS结构中。 通过形成焊盘层并相对于先前存在的CMOS器件的源极和漏极提高本征基极层的高度，并且通过选择性外延形成外部基极，在外部基极的光刻图案化期间，拓扑变化的影响被最小化。 而且，通过在双极结构的制造期间不采用任何化学机械平面化工艺，工艺集成的复杂性降低。 可以形成内部间隔物或外部隔离物以将基底与发射器隔离。 垫层，本征基层和非本征基层形成具有重合的外侧壁表面的台面结构。
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公开(公告)号：US06911681B1
公开(公告)日：2005-06-28
申请号：US10709113
申请日：2004-04-14
申请人： Peter J. Geiss , Alvin J. Joseph , Qizhi Liu , Bradley A. Orner
发明人： Peter J. Geiss , Alvin J. Joseph , Qizhi Liu , Bradley A. Orner
IPC分类号： H01L21/331 , H01L21/8249 , H01L27/06 , H01L29/10 , H01L29/739
CPC分类号： H01L29/0804 , H01L21/8249 , H01L27/0623 , H01L29/1004 , H01L29/66287
摘要： Disclosed is a bipolar complementary metal oxide semiconductor (BiCMOS) or NPN/PNP device that has a collector, an intrinsic base above the collector, shallow trench isolation regions adjacent the collector, a raised extrinsic base above the intrinsic base, a T-shaped emitter above the extrinic base, spacers adjacent the emitter, and a silicide layer that is separated from the emitter by the spacers.
摘要翻译： 公开了一种双极互补金属氧化物半导体（BiCMOS）或NPN / PNP器件，其具有集电极，集电极之上的本征基极，与集电极相邻的浅沟槽隔离区，在本征基极之上的凸起的外部基极，T形发射极 在离子基底之上，邻近发射极的间隔物，以及通过间隔物与发射极分离的硅化物层。
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