公开(公告)号：US11658032B2

公开(公告)日：2023-05-23

申请号：US17205715

申请日：2021-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chin Chen ,  Cheng-Yi Wu ,  Yu-Hung Cheng ,  Ren-Hua Guo ,  Hsiang Liu ,  Chin-Szu Lee

IPC: H01L29/78 ,  H01L21/331 ,  H01L21/20 ,  H01L29/66 ,  H01L29/04 ,  H01L21/02 ,  H01L29/08 ,  H01L29/165 ,  H01L21/306

CPC classification number: H01L21/2022 ,  H01L21/02002 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/0262 ,  H01L21/02381 ,  H01L21/02502 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02636 ,  H01L21/02639 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66287 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848 ,  H01L21/30608

Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.

公开(公告)号：US20190131175A1

公开(公告)日：2019-05-02

申请号：US15797302

申请日：2017-10-30

Applicant: Avago Technologies General IP (Singapore) Pte. Ltd

Inventor： Thomas Edward Dungan ,  Jonathan Kwadwo Abrokwah ,  Forest Dixon ,  William Snodgrass

IPC: H01L21/8249 ,  H01L27/06 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L21/8249 ,  H01L21/823481 ,  H01L21/8252 ,  H01L23/562 ,  H01L27/0605 ,  H01L27/0623 ,  H01L27/0825 ,  H01L29/0813 ,  H01L29/1004 ,  H01L29/66287 ,  H01L29/66666 ,  H01L29/7322 ,  H01L29/7827

Abstract: A transistor module includes a substrate; a transistor on the substrate; a dielectric layer disposed over the transistor and the substrate; a metal layer disposed over the dielectric layer and the transistor, the metal layer contacting a portion of the transistor; a metal pillar disposed over the metal layer; and a dielectric cushion disposed between the metal layer and the metal pillar over the transistor. The dielectric cushion includes dielectric material that is softer than the metal pillar, for reducing strain on semiconductor junctions when at least one of tensile or compressive stress is exerted on the metal pillar with respect to the substrate. The transistor module may further include at least one buttress formed between the metal layer and the substrate, adjacent to the transistor, for further reducing strain on the semiconductor junctions by providing at least one corresponding alterative stress path that substantially bypasses the transistor.

公开(公告)号：US20180175196A1

公开(公告)日：2018-06-21

申请号：US15475826

申请日：2017-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chin Chen ,  Cheng-Yi Wu ,  Yu-Hung Cheng ,  Ren-Hua Guo ,  Hsiang Liu ,  Chin-Szu Lee

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/06 ,  H01L29/161 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L21/2022 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/30608 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66287 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.

公开(公告)号：US20180102422A1

公开(公告)日：2018-04-12

申请号：US15291561

申请日：2016-10-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： ANTHONY K. STAMPER ,  VIBHOR JAIN ,  RENATA A. CAMILLO-CASTILLO

IPC: H01L29/737 ,  H01L29/165 ,  H01L29/06 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L21/7682 ,  H01L23/3171 ,  H01L23/4821 ,  H01L29/41708 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/7378

Abstract: Disclosed are embodiments of a transistor, which incorporates an airgap for low base-emitter capacitance (Cbe). Each embodiment of the transistor has a monocrystalline base and, within the monocrystalline base, an intrinsic base region and an extrinsic base region positioned laterally adjacent to the intrinsic base region, wherein the intrinsic and extrinsic base regions have co-planar top surfaces. An essentially T-shaped emitter in cross-section has a lower emitter region on the intrinsic base region and an upper emitter region above the lower emitter region. Each embodiment of the transistor further has an airgap, which is positioned laterally adjacent to the lower emitter region so as to be between the extrinsic base region and the upper emitter region. Thus, the entire airgap is above the co-planar top surfaces of the intrinsic base region and the extrinsic base region. Also disclosed herein are methods of forming the transistor embodiments.

公开(公告)号：US09859172B1

公开(公告)日：2018-01-02

申请号：US15280068

申请日：2016-09-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brent A. Anderson ,  Kangguo Cheng ,  Terence B. Hook ,  Tak H. Ning

IPC: H01L21/8249 ,  H01L27/06 ,  H01L29/66 ,  H01L29/732 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L23/3171 ,  H01L27/0635 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/0847 ,  H01L29/1004 ,  H01L29/1037 ,  H01L29/42356 ,  H01L29/66272 ,  H01L29/66287 ,  H01L29/66666 ,  H01L29/732 ,  H01L29/7827

Abstract: Integrated chips and methods of forming the same include forming a gate stack around a first semiconductor fin and a second semiconductor fin. The gate stack around the second semiconductor fin is etched away. An extrinsic base is formed around the second semiconductor fin in a region exposed by etching away the gate stack.

公开(公告)号：US09673294B2

公开(公告)日：2017-06-06

申请号：US15063541

申请日：2016-03-08

Applicant: Infineon Technologies Dresden GmbH

Inventor： Dmitri Alex Tschumakow ,  Claus Dahl ,  Armin Tilke

IPC: H01L21/331 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/732 ,  H01L29/737 ,  H01L29/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165

CPC classification number: H01L29/66272 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/165 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/7371 ,  H01L29/7378

Abstract: According to various embodiments, a bipolar transistor structure may include: a substrate; a collector region in the substrate; a base region disposed over the collector region, an emitter region disposed over the base region; a base terminal laterally electrically contacting the base region, wherein the base terminal includes polysilicon.

公开(公告)号：US09490352B2

公开(公告)日：2016-11-08

申请号：US15074633

申请日：2016-03-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kevin K. Chan ,  Bahman Hekmatshoartabari ,  Tak H. Ning

IPC: H01L29/735 ,  H01L29/08 ,  H01L27/06 ,  H01L29/10 ,  H01L29/167

CPC classification number: H01L29/0638 ,  H01L27/06 ,  H01L27/0623 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/167 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66234 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/735 ,  H01L29/7398

Abstract: A method for forming a bipolar junction transistor includes forming a collector intrinsic region, an emitter intrinsic region and an intrinsic base region between the collector intrinsic region and the emitter intrinsic region. A collector extrinsic contact region is formed in direct contact with the collector intrinsic region; an emitter extrinsic contact region is formed on the emitter intrinsic region and a base extrinsic contact region is formed in direct contact with the intrinsic base region. Carbon is introduced into at least one of the collector extrinsic contact region, the emitter extrinsic contact region and the base extrinsic contact region to suppress diffusion of dopants into the junction region.

Abstract translation: 用于形成双极结型晶体管的方法包括在集电极本征区域和发射极本征区域之间形成集电极本征区域，发射极本征区域和本征基极区域。 集电体外部接触区域与集电极本征区域直接接触形成; 在发射极本征区域上形成发射极外部接触区域，并且形成与本征基极区域直接接触的基本非本征接触区域。 将碳引入到集电体外部本征接触区域，发射极非本征接触区域和基本非本征接触区域中的至少一个中，以抑制掺杂剂扩散到接合区域中。

公开(公告)号：US09368608B1

公开(公告)日：2016-06-14

申请号：US14749809

申请日：2015-06-25

Applicant: GLOBALFOUNDARIES INC.

Inventor： Renata Camillo-Castillo ,  Vibhor Jain ,  Vikas K. Kaushal ,  Marwan H. Khater

IPC: H01L29/732 ,  H01L29/66 ,  H01L29/06 ,  H01L29/737 ,  H01L21/764 ,  H01L21/265 ,  H01L29/08

CPC classification number: H01L29/7371 ,  H01L21/26586 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/66287 ,  H01L29/732

Abstract: Fabrication methods for a device structure and device structures. A trench isolation region is formed that bounds an active device region of a semiconductor substrate. A first semiconductor layer is formed on the active device region and on the trench isolation region. A first airgap is formed between the first semiconductor layer and the active device region. A second airgap is formed between the first semiconductor layer and the trench isolation region. The first airgap extends into the active device region such that the height of the first airgap is greater than the height of the second airgap.

Abstract translation: 器件结构和器件结构的制造方法。 形成界定半导体衬底的有源器件区的沟槽隔离区。 在有源器件区域和沟槽隔离区域上形成第一半导体层。 在第一半导体层和有源器件区之间形成第一气隙。 在第一半导体层和沟槽隔离区之间形成第二气隙。 第一气隙延伸到有源装置区域中，使得第一气隙的高度大于第二气隙的高度。

公开(公告)号：US09318551B2

公开(公告)日：2016-04-19

申请号：US14527042

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata Camillo-Castillo ,  Marwan H. Khater

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/732 ,  H01L29/735 ,  H01L29/737 ,  H01L21/76

CPC classification number: H01L29/0653 ,  H01L29/0649 ,  H01L29/66272 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/7325 ,  H01L29/735 ,  H01L29/737

Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first isolation region is formed in a substrate to define a lateral boundary for an active device region and an intrinsic base layer is formed on the substrate. The intrinsic base layer has a section overlying the active device region. After the intrinsic base layer is formed, the first isolation region is partially removed adjacent to the active device region to define a trench that is coextensive with the substrate in the active device region and that is coextensive with the first isolation region. The trench is at least partially filled with a dielectric material to define a second isolation region.

公开(公告)号：US20150287815A1

公开(公告)日：2015-10-08

申请号：US14742979

申请日：2015-06-18

Applicant: Micron Technology, Inc.

Inventor： Badih El-Kareh ,  Leonard Forbes ,  Kie Y. Ahn

IPC: H01L29/732 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/732 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/66287 ,  H01L29/73 ,  H01L29/7371 ,  H03K17/60

Abstract: Methods, devices, and systems for using and forming vertically base-connected bipolar transistors have been shown. The vertically base-connected bipolar transistors in the embodiments of the present disclosure are formed with a CMOS fabrication technique that decreases the transistor size while maintaining the high performance characteristics of a bipolar transistor.

Abstract translation: 已经示出了用于使用和形成垂直基极连接的双极晶体管的方法，装置和系统。 在本公开的实施例中的垂直基极连接的双极晶体管由CMOS制造技术形成，其在保持双极晶体管的高性能特性的同时降低晶体管尺寸。