公开(公告)号：US11099754B1

公开(公告)日：2021-08-24

申请号：US15931867

申请日：2020-05-14

Applicant: EMC IP Holding Company LLC

Inventor： Sanjib Mallick ,  John Krasner ,  Arieh Don ,  Ramesh Doddaiah

IPC: G06F13/00 ,  G06F3/06 ,  G06F9/4401

Abstract: An apparatus comprises at least one processing device comprising a processor coupled to a memory. The at least one processing device is configured to receive, via a multi-path layer of at least one host device, at least one indication of a predicted distribution of input-output operations directed from the at least one host device to a storage system for a given time interval. The at least one processing device is also configured to determine a cache memory configuration for a cache memory associated with the storage system based at least in part on the at least one indication of the predicted distribution of input-output operations for the given time interval. The at least one processing device is further configured to provision the cache memory with the determined cache memory configuration for the given time interval.

公开(公告)号：US10884935B1

公开(公告)日：2021-01-05

申请号：US16587286

申请日：2019-09-30

Applicant: EMC IP Holding Company LLC

Inventor： Ramesh Doddaiah

IPC: G06F12/0862

Abstract: A metadata structure of a storage array stores metadata associated with a plurality of prior input-output operations. The metadata comprises an indication of which of the controller boards was utilized to service a prior input-output operation and an input-output size for the prior input-output operation. A given input-output operation is obtained and a target controller board and a target portion of the storage array are identified based at least in part on the given input-output operation. A given controller board is determined to have a higher likelihood of receiving a future input-output operation than at least one other controller board based at least in part on the metadata and a portion of the cache is allocated to the given controller board for storing target data associated with the given input-output operation. The target controller board utilizes the portion of the cache allocated to the given controller board to service the input-output operation.

公开(公告)号：US20200125412A1

公开(公告)日：2020-04-23

申请号：US16165523

申请日：2018-10-19

Applicant: EMC IP HOLDING COMPANY LLC

Inventor： Sweetesh Singh ,  Ramesh Doddaiah

IPC: G06F9/50 ,  G06F3/06

Abstract: Allocation of storage array hardware resources between host-visible and host-hidden services is managed to ensure that sufficient hardware resources are allocated to host-visible services. Information obtained from monitoring real-world operation of the storage array is used to generate a model of the storage array. The generated model represents temporal dependencies between storage array hardware, host-visible services, and host-hidden services. Because the model includes information gathered over time and represents temporal dependencies, future occurrence of repeating variations of storage-related service usage and requirements can be predicted. The model may be used to generate hardware recommendations and dynamically re-allocate existing hardware resources to more reliably satisfy a predetermined level of measured performance.

公开(公告)号：US11880576B2

公开(公告)日：2024-01-23

申请号：US17160526

申请日：2021-01-28

Applicant: EMC IP Holding Company LLC

Inventor： Ramesh Doddaiah ,  Steve Lathrop ,  Anoop Raghunathan ,  Jeremy O'Hare

IPC: G06F3/06

CPC classification number: G06F3/0641 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0689

Abstract: Aspects of the present disclosure relate to data deduplication (dedup) techniques for storage arrays. In embodiments, a sequence of input/output (IO) operations in an IO stream received from one or more host devices by a storage array are identified. Additionally, a determination can be made as to whether a set of previously received IO operations match the identified IO sequence based on a time series relationship between the identified IO sequence and the previously received IO operations. Further, one or more data deduplication (dedup) techniques can be performed on the matching IO sequence.

公开(公告)号：US11625327B2

公开(公告)日：2023-04-11

申请号：US16709013

申请日：2019-12-10

Applicant: EMC IP Holding Company LLC

Inventor： John Krasner ,  Ramesh Doddaiah

IPC: G06F12/0862 ,  G06N3/04 ,  G06F12/0893

Abstract: Embodiments of the present disclosure relate to cache memory management. Based on anticipated input/output (I/O) workloads, at least one or more of: sizes of one or more mirrored and un-mirrored caches of global memory and their respective cache slot pools are dynamically balanced. Each of the mirrored/unmirrored caches can be segmented into one or more cache pools, each having slots of a distinct size. Cache pool can be assigned an amount of the one or more cache slots of the distinct size based on the anticipated I/O workloads. Cache pools can be further assigned the amount of distinctly sized cache slots based on expected service levels (SLs) of a customer. Cache pools can also be assigned the amount of the distinctly sized cache slots based on one or more of predicted I/O request sizes and predicted frequencies of different I/O request sizes of the anticipated I/O workloads.

公开(公告)号：US11467906B2

公开(公告)日：2022-10-11

申请号：US16530682

申请日：2019-08-02

Applicant: EMC IP Holding Company LLC

Inventor： Ramesh Doddaiah ,  Bernard A. Mulligan, III

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F13/12 ,  G06F3/06

Abstract: An apparatus comprises a storage system comprising at least one processing device and a plurality of storage devices. The at least one processing device is configured to obtain a given input-output operation from a host device and to determine that the given input-output operation comprises an indicator having a particular value. The particular value indicates that the given input-output operation is a repeat of a prior input-output operation. The at least one processing device is further configured to rebuild at least one resource of the storage system that is designated for servicing the given input-output operation based at least in part on the determination that the given input-output operation comprises the indicator having the particular value.

公开(公告)号：US11429294B2

公开(公告)日：2022-08-30

申请号：US16881107

申请日：2020-05-22

Applicant: EMC IP HOLDING COMPANY LLC

Inventor： Ramesh Doddaiah ,  Anoop Raghunathan

IPC: G06F3/00 ,  G06F3/06

Abstract: In a data storage system in which a full-size allocation unit is used for storage of uncompressed data, an optimal reduced size allocation unit is selected for storage of compressed data. Changes in the compressed size of at least one full-size allocation unit of representative data are monitored over time. The representative data may be selected based on write frequency, relocation frequency, or both. Compression size values are counted and weighted to calculate the optimal reduced allocation unit size. The optimal reduced size allocation unit is used for storage of compressed data. A full-size allocation unit of data that cannot be accommodated by a reduced size allocation unit when compressed is stored uncompressed.

公开(公告)号：US20210096997A1

公开(公告)日：2021-04-01

申请号：US16589225

申请日：2019-10-01

Applicant: EMC IP Holding Company LLC

Inventor： John Krasner ,  Ramesh Doddaiah

IPC: G06F12/0871 ,  G06F3/06

Abstract: Embodiments of the present disclosure relate to an apparatus comprising a memory and at least one processor. The at least one processor is configured to: analyze input/output (I/O) operations received by a storage system; dynamically predict anticipated I/O operations of the storage system based on the analysis; and dynamically control a size of a local cache of the storage system based on the anticipated I/O operations.

公开(公告)号：US20200334155A1

公开(公告)日：2020-10-22

申请号：US16386795

申请日：2019-04-17

Applicant: EMC IP Holding Company LLC

Inventor： Malak Alshawabkeh ,  Steven John Ivester ,  Ramesh Doddaiah ,  Kaustubh S. Sahasrabudhe

IPC: G06F12/0862 ,  G06N3/08

Abstract: The described technology is generally directed towards caching and aggregated write operations based on predicted patterns of data transfer operations. According to an embodiment, a system can comprise a memory that can store computer executable components, and a processor that can execute the computer executable components stored in the memory. The components can comprise a pattern identifying component to identify a first pattern of data transfer operations performed on a data store, resulting in an identified first pattern, based on monitored data transfer operations. The components can further comprise a pattern predicting component to predict a second pattern of future data transfer operations performed on the data store, resulting in a predicted second pattern, based on the identified first pattern. The components can further comprise a host adapter to generate a data transfer operation to be performed on the data store based on the predicting the second pattern.