公开(公告)号：US20140162683A1

公开(公告)日：2014-06-12

申请号：US13712043

申请日：2012-12-12

Applicant: Haim Rochberger ,  Yaron Alpert ,  Ehud Reshef

Inventor： Haim Rochberger ,  Yaron Alpert ,  Ehud Reshef

IPC: H04W64/00

CPC classification number: H04W64/00 ,  G01S5/0236

Abstract: Some demonstrative embodiments include devices, systems and/or methods of estimating a location of a mobile device. For example, a location estimation entity (LE) may be configured to receive from a server location-based location-enabling source (LES) information identifying one or more location-enabling sources based on a location area of a mobile device, and to communicate with the one or more identified location-enabling sources information for estimating the location of the mobile device.

Abstract translation: 一些演示实施例包括估计移动设备的位置的设备，系统和/或方法。 例如，位置估计实体（LE）可以被配置为基于移动设备的位置区域从服务器接收基于位置的位置使能源（LES）信息来识别一个或多个位置使能源，并且通信 所述一个或多个识别的位置使能源信息用于估计移动设备的位置。

公开(公告)号：US07307977B1

公开(公告)日：2007-12-11

申请号：US10262691

申请日：2002-10-01

Applicant: Alon Eran ,  Yaniv Avital ,  Ehud Reshef

Inventor： Alon Eran ,  Yaniv Avital ,  Ehud Reshef

IPC: H04J13/02

CPC classification number: H04W52/54 ,  H04B1/7117 ,  H04B2201/70701 ,  H04W52/56 ,  H04W52/58

Abstract: A real-time optimizing information transfer and interrupt event scheduling scheme for a communications transceiver incorporating multiple processing elements. The scheme is particularly applicable for use in UMTS based communications transceivers, i.e. W-CDMA transceivers adapted for User Equipment (UE). The interrupt scheduling scheme of the present invention is operative to perform the scheduling of interrupts used to configure a data transfer device to effect the timely transfer of data from a hardware based chip rate processor to a memory buffer for subsequent processing by software running on a DSP or other processor platform.

Abstract translation: 实时优化信息传输和中断事件调度方案，用于包含多个处理元件的通信收发器。 该方案特别适用于基于UMTS的通信收发机，即适用于用户设备（UE）的W-CDMA收发器。 本发明的中断调度方案可用于执行用于配置数据传输设备的中断的调度，以便将数据从基于硬件的码片速率处理器及时传送到存储器缓冲器，以便随后在DSP上运行的软件 或其他处理器平台。

公开(公告)号：US07039134B1

公开(公告)日：2006-05-02

申请号：US10050968

申请日：2002-01-22

Applicant: Yaniv Avital ,  Ehud Reshef

Inventor： Yaniv Avital ,  Ehud Reshef

IPC: H04L27/06

CPC classification number: H04B1/707 ,  H04B1/7095 ,  H04B1/7115 ,  H04B2201/70711

Abstract: A reduced complexity correlator that enables the re-use of the most complex portions of a correlator, namely the multiplier and adder. The correlator of the present invention is especially well-suited for use in CDMA and W-CDMA spread spectrum communication systems that require the use of numerous correlators in their operation. Multiple input samples, multiple codes and integration results are stored in shift registers and circularly shifted and clocked out at appropriate clock rates such that the multiplication and accumulation steps of the correlation process are synchronized.

Abstract translation: 一种降低的复杂度相关器，其能够重新使用相关器的最复杂部分，即乘法器和加法器。 本发明的相关器特别适用于需要在其操作中使用大量相关器的CDMA和W-CDMA扩频通信系统。 多个输入样本，多个代码和积分结果存储在移位寄存器中，并以适当的时钟速率循环移位和计时，使得相关处理的乘法和累加步骤同步。

公开(公告)号：US06993541B2

公开(公告)日：2006-01-31

申请号：US10827594

申请日：2004-04-19

Applicant: Ehud Reshef ,  Idan Alrod

Inventor： Ehud Reshef ,  Idan Alrod

IPC: G06F17/14

CPC classification number: G06F17/145

Abstract: A method and apparatus for performing a radix-4 fast Hadamard transform (FHT) with reduced complexity and for directly determining the maximum output of a fast Hadamard transform using either a radix-4 transform or radix-2 transform without actually generating the outputs. The radix-4 fast Hadamard transform is implemented using only seven operations. To find the maximum value of the output of a fast Hadamard transform and its corresponding index, the N-1 stages of a conventional N stage fast Hadamard transform are computed while a find-maximum stage is inserted in place of the Nth stage. The invention also provides a methodology for constructing fast Hadamard transforms of the form H2N using radix-4 FHTs and permuting the results to achieve the correct outputs.

Abstract translation: 一种方法和装置，用于以降低的复杂度执行基4快速Hadamard变换（FHT），并且使用基数-4变换或基数-2变换直接确定快速哈达玛变换的最大输出，而不实际产生输出。 基数4快速Hadamard变换仅使用七个操作实现。 为了找到快速Hadamard变换的输出的最大值及其对应的索引，计算常规N阶段快速Hadamard变换的N-1阶段，同时插入找到最大阶段代替N < 舞台。 本发明还提供了一种用于使用基数-4 FHT来构建H 2形式的快速Hadamard变换的方法，并将结果置换以实现 正确的输出。

公开(公告)号：US06901121B1

公开(公告)日：2005-05-31

申请号：US09789437

申请日：2001-02-20

Applicant: Andrew Dubrovin ,  Evgeny Yakhnich ,  Ehud Reshef

Inventor： Andrew Dubrovin ,  Evgeny Yakhnich ,  Ehud Reshef

IPC: H03D1/06 ,  H03D3/00 ,  H04K1/00 ,  H04L25/02 ,  H04L25/06 ,  H03D1/03 ,  H04K25/08 ,  H09K5/01 ,  H09K6/04

CPC classification number: H03D3/008 ,  H04L25/0228 ,  H04L25/063

Abstract: A novel and useful apparatus for and method of DC offset compensation for use in a communications receiver. The invention is operative to calculate an estimate of the DC offset which is subsequently subtracted from each input sample to generate compensated samples. The training sequence portion of the uncompensated input samples is used to generate an estimate of the DC offset. The vector used in calculating the offset estimate is pre-calculated for several channel lengths and stored in memory. An estimate of the channel is generated which provides the channel length and the location in the input sample buffer of the first training sequence sample to be used in calculating the offset estimate. The channel length is used to determine the number of training sequence samples to be used and to select one of the previously calculated vectors.

Abstract translation: 一种用于通信接收机中的DC偏移补偿的新颖有用的装置和方法。 本发明可操作以计算DC偏移的估计，其随后从每个输入样本中减去以产生补偿样本。 未补偿输入样本的训练序列部分用于产生DC偏移的估计。 用于计算偏移估计的矢量被预先计算出几个通道长度并存储在存储器中。 生成信道的估计，其提供要在计算偏移估计中使用的第一训练序列样本的输入采样缓冲器中的信道长度和位置。 通道长度用于确定要使用的训练序列样本的数量，并选择先前计算的向量之一。