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    BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 4/15 AND 1024-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME
    32.
    发明申请
    BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 4/15 AND 1024-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME 审中-公开
    用于低密度奇偶校验的比特交换机检查长度为64800，编码速率为4/15和1024符号映射，以及使用相同的位交互方法

    公开(公告)号：US20160241265A1

    公开(公告)日：2016-08-18

    申请号：US14664718

    申请日：2015-03-20

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Sung-Ik PARK ,  Sun-Hyoung KWON ,  Jae-Young LEE ,  Heung-Mook KIM ,  Nam-Ho HUR

    IPC: H03M13/27 ,  H03M13/11

    CPC classification number: H03M13/1165 ,  H03M13/255 ,  H03M13/271 ,  H03M13/2778

    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 1024-symbol mapping.

    Abstract translation: 本文公开了一种位交织器，位交织编码调制（BICM）装置和比特交织方法。 比特交织器包括第一存储器，处理器和第二存储器。 第一存储器存储长度为64800和码率为4/15的低密度奇偶校验（LDPC）码字。 处理器通过基于比特组交织LDPC码字来产生交错码字。 位组的大小对应于LDPC码字的并行因子。 第二存储器将交织的码字提供给用于1024符号映射的调制器。

    BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 3/15 AND 256-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME
    33.
    发明申请
    BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 3/15 AND 256-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME 审中-公开
    用于低密度奇偶校验的比特交换机检查长度为64800，编码速率为3/15和256符号映射，以及使用相同的比特交换方法

    公开(公告)号：US20160241262A1

    公开(公告)日：2016-08-18

    申请号：US14639625

    申请日：2015-03-05

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Sung-Ik PARK ,  Sun-Hyoung KWON ,  Jae-Young LEE ,  Heung-Mook KIM ,  Nam-Ho HUR

    IPC: H03M13/27 ,  H03M13/11

    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

    Abstract translation: 本文公开了一种位交织器，位交织编码调制（BICM）装置和比特交织方法。 比特交织器包括第一存储器，处理器和第二存储器。 第一存储器存储长度为64800且码率为3/15的低密度奇偶校验（LDPC）码字。 处理器通过基于比特组交织LDPC码字来产生交错码字。 位组的大小对应于LDPC码字的并行因子。 第二存储器将交织的码字提供给用于256符号映射的调制器。

    BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 3/15 AND 1024-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME
    36.
    发明申请
    BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 3/15 AND 1024-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME 审中-公开
    用于低密度奇偶校验的比特交换机检查长度为64800的长度和3/15和1024符号映射的代码率，以及使用相同的位交互方法

    公开(公告)号：US20150270854A1

    公开(公告)日：2015-09-24

    申请号：US14664712

    申请日：2015-03-20

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Sung-Ik PARK ,  Sun-Hyoung KWON ,  Jae-Young LEE ,  Heung-Mook KIM ,  Nam-Ho HUR

    IPC: H03M13/27 ,  H03M13/09

    CPC classification number: H03M13/036 ,  H03M13/1165 ,  H03M13/255 ,  H03M13/2778

    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 1024-symbol mapping.

    Abstract translation: 本文公开了一种位交织器，位交织编码调制（BICM）装置和比特交织方法。 比特交织器包括第一存储器，处理器和第二存储器。 第一存储器存储长度为64800且码率为3/15的低密度奇偶校验（LDPC）码字。 处理器通过基于比特组交织LDPC码字来产生交错码字。 位组的大小对应于LDPC码字的并行因子。 第二存储器将交织的码字提供给用于1024符号映射的调制器。

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