公开(公告)号：US20120242594A1

公开(公告)日：2012-09-27

申请号：US13239905

申请日：2011-09-22

申请人： Takashi MATSUMOTO

发明人： Takashi MATSUMOTO

IPC分类号： G08C21/00 ,  G06F3/041

CPC分类号： G06F1/1626 ,  G06F1/1643 ,  G06F3/0484 ,  G06F3/0488

摘要： An input device includes a body unit, a first touch type position detection unit which detects a first touch position of a human body on a first detection surface of the body unit, a second touch type position detection unit which detects a second touch position of the human body on a second detection surface of the body unit, the second detection surface being on an opposite side of the body unit as the first detection surface, and a detection area restriction unit which restricts an area, which can be detected by the second touch type position detection unit, on the second detection surface according to information of the first touch position and information determined in advance. The information determined in advance is data indicating a relation between the first touch position on the first detection surface and the restricted area on the second detection surface.

摘要翻译： 输入装置包括主体单元，第一触摸型位置检测单元，其检测身体单元的第一检测表面上的人体的第一触摸位置;第二触摸式位置检测单元，其检测第二触摸位置检测单元 人体在身体单元的第二检测表面上，第二检测表面与身体单元的与第一检测表面相反的一侧，以及检测区域限制单元，其限制可以由第二触摸检测的区域 类型位置检测单元，根据第一触摸位置的信息和预先确定的信息在第二检测表面上。 预先确定的信息是指示第一检测表面上的第一触摸位置与第二检测表面上的限制区域之间的关系的数据。

公开(公告)号：US20090106718A1

公开(公告)日：2009-04-23

申请号：US12253469

申请日：2008-10-17

申请人： Takashi MATSUMOTO ,  Junji Noguchi ,  Takayuki Oshima

发明人： Takashi MATSUMOTO ,  Junji Noguchi ,  Takayuki Oshima

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  H01L21/7682 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a method for manufacturing a semiconductor integrated circuit device which enables a timing optimization without giving additions to a manufacturing process and increasing cost and TAT. Existence of a timing constraint violation is determined, and when a timing constraint violation is detected, to dissolve the violation, a void formation inhibition zone is set up in a part or all of a spacing (inter-wiring spacing) between an optimization-target wiring which needs a further delay time of a signal and clock and an adjacent wiring adjacent to the optimization-target wiring having a spacing within a specified wiring spacing, and an insulating film is formed in a spacing (inter-wiring spacing) between the optimization-target wiring and the adjacent wiring in the void formation inhibition zone, and voids are formed in a spacing (inter-wiring spacing) between the optimization-target wiring and the adjacent wiring outside the void formation inhibition zone.

摘要翻译： 提供一种制造半导体集成电路器件的方法，其能够进行定时优化，而不增加制造工艺并增加成本和TAT。 确定定时约束违规的存在，并且当检测到定时约束违规时，为了解决违规，在优化目标之间的间隔（布线间距）的一部分或全部中建立空隙形成禁止区 需要进一步延迟信号和时钟的延迟时间的布线以及与优选目标布线相邻的相邻布线，其间距在指定布线间距内，并且绝缘膜以优选的间隔（布线间距）形成 在空隙形成抑制区域中的目标布线和相邻布线，并且在空隙形成抑制区外部的优化目标布线和相邻布线之间的间隔（布线间距）形成空隙。