公开(公告)号：US10284744B2

公开(公告)日：2019-05-07

申请号：US15598933

申请日：2017-05-18

Applicant: Google LLC

Inventor： Albert Meixner ,  Jason Rupert Redgrave ,  Ofer Shacham ,  Qiuling Zhu ,  Daniel Frederic Finchelstein

IPC: H04N1/32 ,  G06T1/60 ,  B41F15/08

Abstract: A sheet generator circuit is described. The sheet generator includes electronic circuitry to receive a line group of image data including multiple rows of data from a frame of image data. The multiple rows are sufficient in number to encompass multiple neighboring overlapping stencils. The electronic circuitry is to parse the line group into a smaller sized sheet. The electronic circuitry is to load the sheet into a data computation unit having a two dimensional shift array structure coupled to an array of processors.

公开(公告)号：US10277833B2

公开(公告)日：2019-04-30

申请号：US15479159

申请日：2017-04-04

Applicant: Google LLC

Inventor： Qiuling Zhu ,  Ofer Shacham ,  Jason Rupert Redgrave ,  Daniel Frederic Finchelstein ,  Albert Meixner

IPC: G09G5/36 ,  H04N5/262 ,  G06T1/60 ,  G06T1/20

Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S−1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.

公开(公告)号：US10216487B2

公开(公告)日：2019-02-26

申请号：US15591984

申请日：2017-05-10

Applicant: Google LLC

Inventor： Albert Meixner ,  Ofer Shacham ,  David Patterson ,  Daniel Frederic Finchelstein ,  Qiuling Zhu ,  Jason Rupert Redgrave

IPC: G06F8/10 ,  G06F8/20 ,  G06F9/30 ,  G06T1/20 ,  G06F17/50

Abstract: A method is described that includes instantiating, within an application software development environment, a virtual processor having an instruction set architecture and memory model that contemplate first and second regions of reserved memory. The first reserved region is to keep data of an input image array. The second reserved region is to keep data of an output image array. The method also includes simulating execution of a memory load instruction of the instruction set architecture by automatically targeting the first reserved region and identifying desired input data with first and second coordinates relative to the virtual processor's position within an orthogonal coordinate system and expressed in the instruction format of the memory load instruction.

公开(公告)号：US10204396B2

公开(公告)日：2019-02-12

申请号：US15427374

申请日：2017-02-08

Applicant: GOOGLE LLC

Inventor： Albert Meixner ,  Hyunchul Park ,  Qiuling Zhu ,  Jason Rupert Redgrave

IPC: G09G3/36 ,  G06T1/60 ,  G06F9/38 ,  G06T1/20

Abstract: A method is described. The method includes repeatedly loading a next sheet of image data from a first location of a memory into a two dimensional shift register array. The memory is locally coupled to the two-dimensional shift register array and an execution lane array having a smaller dimension than the two-dimensional shift register array along at least one array axis. The loaded next sheet of image data keeps within an image area of the two-dimensional shift register array. The method also includes repeatedly determining output values for the next sheet of image data through execution of program code instructions along respective lanes of the execution lane array, wherein, a stencil size used in determining the output values encompasses only pixels that reside within the two-dimensional shift register array. The method also includes repeatedly moving a next sheet of image data to be fully loaded into the two dimensional shift register array from a second location of the memory to the first location of the memory.

公开(公告)号：US10095479B2

公开(公告)日：2018-10-09

申请号：US14694890

申请日：2015-04-23

Applicant: Google LLC

Inventor： Albert Meixner ,  Ofer Shacham ,  David Patterson ,  Daniel Frederic Finchelstein ,  Qiuling Zhu ,  Jason Rupert Redgrave

IPC: G06F8/20 ,  G06F8/10 ,  G06T1/20 ,  G06F9/30

Abstract: A method is described that includes instantiating, within an application software development environment, a virtual processor having an instruction set architecture and memory model that contemplate first and second regions of reserved memory. The first reserved region is to keep data of an input image array. The second reserved region is to keep data of an output image array. The method also includes simulating execution of a memory load instruction of the instruction set architecture by automatically targeting the first reserved region and identifying desired input data with first and second coordinates relative to the virtual processor's position within an orthogonal coordinate system and expressed in the instruction format of the memory load instruction.