公开(公告)号：US07596038B2

公开(公告)日：2009-09-29

申请号：US11954468

申请日：2007-12-12

申请人： Hoki Kim ,  Geng Wang

发明人： Hoki Kim ,  Geng Wang

IPC分类号： G11C11/406 ,  G11C11/24

CPC分类号： G11C11/406 ,  G11C2211/4016 ,  G11C2211/4065

摘要： A system including a DRAM memory device on an integrated circuit (IC) using a control logic device to initiate a body refresh operation to provide a means for maintaining a low voltage at a floating body and discourage data loss, and a design structure including the DRAM memory device embodied in a machine readable medium is provided. A plurality of DRAM cells are connected to a first word line circuit and a first bit line circuit. The control logic device is coupled to the DRAM memory device and the IC for initiating the body refresh cycle. The control logic communicates with a first bit line and word line circuits and communicates with a reference word line and bit line circuits. A sense amplifier circuit and signal is provided for amplifying the voltage at the first bit line and the reference bit line. The body refresh cycle includes deactivating the first word line voltage while the first bit line and reference bit line voltages continue.

摘要翻译： 一种系统，包括使用控制逻辑装置的集成电路（IC）上的DRAM存储器件，以启动身体刷新操作，以提供用于在浮体保持低电压并阻止数据丢失的装置，以及包括DRAM的设计结构 提供了体现在机器可读介质中的存储设备。 多个DRAM单元连接到第一字线电路和第一位线电路。 控制逻辑器件耦合到DRAM存储器件和用于启动器件刷新周期的IC。 控制逻辑与第一位线和字线电路通信，并与参考字线和位线电路进行通信。 提供读出放大器电路和信号用于放大第一位线和参考位线处的电压。 身体刷新周期包括在第一位线和参考位线电压持续时停用第一字线电压。

公开(公告)号：US20080084774A1

公开(公告)日：2008-04-10

申请号：US11534070

申请日：2006-09-21

申请人： Hoki Kim ,  Geng Wang

发明人： Hoki Kim ,  Geng Wang

IPC分类号： G11C11/24 ,  G11C7/00

CPC分类号： G11C11/406 ,  G11C11/404 ,  G11C2211/4016

摘要： A system and method wherein a DRAM memory device on an integrated circuit (IC) uses a control logic device to initiate a body refresh operation to provide a means for maintaining a low voltage at a floating body and discourage data loss. A plurality of DRAM cells are connected to a first word line circuit and a first bit line circuit. The control logic device is coupled to the DRAM memory device and the IC for initiating the body refresh cycle. The control logic communicates with a first bit line and word line circuits and communicates with a reference word line and bit line circuits. A sense amplifier circuit and signal is provided for amplifying the voltage at the first bit line and the reference bit line. The body refresh cycle includes deactivating the first word line voltage while the first bit line and reference bit line voltages continue.

摘要翻译： 一种系统和方法，其中集成电路（IC）上的DRAM存储器件使用控制逻辑器件来启动主体刷新操作，以提供用于在浮体保持低电压并且阻止数据丢失的装置。 多个DRAM单元连接到第一字线电路和第一位线电路。 控制逻辑器件耦合到DRAM存储器件和用于启动器件刷新周期的IC。 控制逻辑与第一位线和字线电路通信，并与参考字线和位线电路进行通信。 提供读出放大器电路和信号用于放大第一位线和参考位线处的电压。 身体刷新周期包括在第一位线和参考位线电压持续时停用第一字线电压。