公开(公告)号：US09697311B2

公开(公告)日：2017-07-04

申请号：US15367276

申请日：2016-12-02

Applicant: International Business Machines Corporation

Inventor： Zhaoqing Chen

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/504 ,  G06F17/5045 ,  G06F2217/36

Abstract: A method to generate a reduced delay twinaxial SPICE model is provided. The method may include measuring near-end S-parameter components and far-end S-parameter components of a twinaxial cable, reducing an original time delay of the far-end S-parameter components by multiplying each of the far-end S-parameter components by a complex exponential based on an equivalent delay length, a signal frequency, and an effective dielectric constant, simulating a signal transmitted across a twinaxial cable by running a 4-port SPICE model using the near-end S-parameter components and the multiplied far-end S-parameter components, and recording a magnitude and a phase of the transmitted signal with respect to frequency as outputs of the reduced delay twinaxial SPICE model.

公开(公告)号：US20170048967A1

公开(公告)日：2017-02-16

申请号：US15336884

申请日：2016-10-28

Applicant: International Business Machines Corporation

Inventor： Zhaoqing Chen ,  Matteo Cocchini ,  Rohan U. Mandrekar ,  Tingdong Zhou

IPC: H05K1/02 ,  H01L23/66 ,  H01L23/528 ,  H01P3/08 ,  H01P3/02

CPC classification number: H01L23/49838 ,  H01L23/528 ,  H01L23/66 ,  H01L2223/6627 ,  H01P3/02 ,  H01P3/026 ,  H01P3/081 ,  H04B1/00 ,  H04B3/32 ,  H05K1/0216 ,  H05K1/0245

Abstract: An electronic device including a plurality of interconnects are orthogonally arranged in a grid pattern and evenly spaced by a first distance, the plurality of interconnects include: a first conductor pair with conductors arranged next to each other in a first direction, the first direction is oriented diagonally relative to the orthogonal grid pattern, a second conductor pair with conductors arranged next to each other in a second direction substantially perpendicular to the first direction, each conductor of the second conductor pair is spaced by the first distance from each signal conductor of the first conductor pair, and a third conductor pair with conductors arranged next to each other in a third direction substantially parallel to the first direction, each conductors of the third conductor pair is spaced by the first distance from one of the signal elements of the second conductor pair.

Abstract translation: 包括多个互连件的电子设备以网格图案正交布置并均匀间隔第一距离，所述多个互连件包括：第一导体对，其具有沿第一方向彼此相邻布置的导体，所述第一方向定向 相对于正交栅格图案的对角线的第二导体对，具有基本上垂直于第一方向的第二方向彼此相邻布置的导体的第二导体对，第二导体对的每个导体与第一导体对的每个信号导体间隔开第一距离 导体对和第三导体对，其中导体在基本上平行于第一方向的第三方向上彼此相邻布置，第三导体对的每个导体与第二导体对的信号元件之一间隔开第一距离 。

公开(公告)号：US20170006709A1

公开(公告)日：2017-01-05

申请号：US14859382

申请日：2015-09-21

Applicant: International Business Machines Corporation

Inventor： Zhaoqing Chen ,  Matteo Cocchini ,  Rohan Mandrekar ,  Tingdong Zhou

IPC: H05K3/30

CPC classification number: G06F17/5072 ,  G06F2217/82 ,  H01G4/06 ,  H01G4/224 ,  H01G13/00 ,  H05K1/0231 ,  H05K1/162

Abstract: In one embodiment, a method includes positioning a first signal pad in a first layer of a printed circuit board and positioning a second signal pad in a second layer of the printed circuit board. The second signal pad is positioned to form an embedded capacitance between the first signal pad and the second signal pad. The embedded capacitance between the first signal pad and the second signal pad is configured to carry a signal between the first layer and the second layer absent a signal via.