公开(公告)号：US11539532B2

公开(公告)日：2022-12-27

申请号：US17038298

申请日：2020-09-30

Applicant: Infineon Technologies AG

Inventor： Alexander Zeh ,  Wieland Fischer ,  Stefan Koeck

IPC: H04L9/08 ,  H04L9/32

Abstract: A device is suggested including a cryptographic module, wherein the device is operable in a secure mode and in a non-secure mode, wherein the cryptographic module is configured in the secure mode by storing a secret key and a seed value in the cryptographic module, and wherein the device is operable in the non-secure mode to generate a signature based on input data utilizing the secret key and the seed value. Also, a method for operating such device is provided.

公开(公告)号：US11438154B2

公开(公告)日：2022-09-06

申请号：US16949013

申请日：2020-10-09

Applicant: Infineon Technologies AG

Inventor： Muhammad Hassan ,  Bernhard Rohfleisch ,  Alexander Zeh

IPC: H04L9/08 ,  H04L9/06 ,  G06F12/0888 ,  G06F12/14 ,  H04L9/14 ,  H04L9/32 ,  G06F21/60 ,  G06F12/0802

Abstract: A data cryptographic device may include a pre-tweak generator to generate pre-tweak values, a pre-tweak value cache memory to store one or more pre-tweak values generated by the pre-tweak generator, and a pre-tweak value selector to check whether a pre-tweak value for an input memory address is stored in the pre-tweak value cache memory. The data cryptographic device may further include a tweak generator to generate a tweak value based on the selected pre-tweak value, and a block cipher to perform at least one block cipher algorithm to at least one of encrypt data, encrypt and authenticate data, decrypt encrypted data, decrypt and verify encrypted and authenticated data, using a cryptographic key and the generated tweak value.

公开(公告)号：US11362823B2

公开(公告)日：2022-06-14

申请号：US16947725

申请日：2020-08-13

Applicant: Infineon Technologies AG

Inventor： Viola Rieger ,  Alexander Zeh

IPC: H04L29/06 ,  H04L9/16 ,  H04L9/08

Abstract: A device is provided comprising a first memory for storing a first key, a second memory for storing a second key, the device being capable of conducting a first cryptographic algorithm, wherein the first cryptographic algorithm uses the first key, the device being capable of conducting a second cryptographic algorithm, wherein the second cryptographic algorithm uses the second key, and a selection unit, which is programmable to use either the first cryptographic algorithm or the second cryptographic algorithm. Also, a method for operating such device is provided.

公开(公告)号：US11308240B2

公开(公告)日：2022-04-19

申请号：US16051775

申请日：2018-08-01

Applicant: Infineon Technologies AG

Inventor： Alexander Zeh ,  Viola Rieger ,  Klaus Scheibert

IPC: G06F21/72 ,  H04L9/08 ,  G06F21/60 ,  G09C1/00 ,  G06F7/58

Abstract: A method for cryptographic data processing by means of a circuit comprises using a first circuit section to perform a first cryptographic operation in order to obtain first cryptographic data. The method further includes transmitting the first cryptographic data to a second circuit section via a transmission area of the circuit that physically separates the second circuit section from the first circuit section and whose resistance to attacks is at most as high as the resistance of the first circuit section. The method includes using the second circuit section to perform a second cryptographic operation using the first cryptographic data in order to obtain second cryptographic data.

公开(公告)号：US11165794B2

公开(公告)日：2021-11-02

申请号：US16588528

申请日：2019-09-30

Applicant: Infineon Technologies AG

Inventor： Alexander Zeh ,  Karel Heurtefeux

IPC: G06F21/00 ,  H04L29/06 ,  H04L9/08 ,  H04L29/12

Abstract: A sender device may include a transmitter and one or more processors. The one or more processors may be configured to transmit, to one or more receiver devices, a frame via a communication bus. The one or more processors may be configured to detect a replicated frame on the communication bus, and identify an attack event based on detecting the replicated frame. The one or more processors may be configured to determine a sequence of interframe transmit times based on identifying the attack event, wherein the sequence of interframe transmit times is determined based on a shared secret associated with the one or more receiver devices. The one or more processors may be configured to transmit a series of alert frames according to the sequence of interframe transmit times to permit the one or more receiver devices to be notified of the attack event.

公开(公告)号：US20200092098A1

公开(公告)日：2020-03-19

申请号：US16134202

申请日：2018-09-18

Applicant: Infineon Technologies AG

Inventor： Alexander Zeh ,  Viola Rieger

IPC: H04L9/08 ,  G06F21/72

Abstract: A Cryptographic Unit (CU) of a microcontroller, the CU including a first accelerator configured to generate first encrypted output data based on input data; and a second accelerator which is configured to be diversely implemented with respect to the first accelerator, and is configured to generate second encrypted output data based on the input data; and a comparator configured to compare a first comparator data obtained from the generation of the first encrypted output data with a second comparator data obtained from the generation of the second encrypted output data, and if the comparison indicates that the first and second comparator data differ, output an event signal pertaining to an event in a safety domain or a security domain.

公开(公告)号：US20190114430A1

公开(公告)日：2019-04-18

申请号：US16161440

申请日：2018-10-16

Applicant: Infineon Technologies AG

Inventor： Alexander Zeh ,  Viola Rieger

IPC: G06F21/57 ,  G06F9/445

Abstract: A method for processing data in a plurality of processing acts includes: configuring a plurality of processing circuits in a first configuration, in such a way that both a first and a second of the plurality of processing circuits execute a first of the plurality of processing acts; and configuring the plurality of processing circuits in a second configuration, in such a way that the first processing circuit executes a second processing act and the second processing circuit executes a third processing act, which is different than the second processing act. An apparatus is designed for carrying out the method.

公开(公告)号：US20190050601A1

公开(公告)日：2019-02-14

申请号：US16051775

申请日：2018-08-01

Applicant: Infineon Technologies AG

Inventor： Alexander Zeh ,  Viola Reiger ,  Klaus Scheibert

IPC: G06F21/72 ,  H04L9/08 ,  G06F7/58

Abstract: A method for cryptographic data processing by means of a circuit comprises using a first circuit section to perform a first cryptographic operation in order to obtain first cryptographic data. The method further includes transmitting the first cryptographic data to a second circuit section via a transmission area of the circuit that physically separates the second circuit section from the first circuit section and whose resistance to attacks is at most as high as the resistance of the first circuit section. The method includes using the second circuit section to perform a second cryptographic operation using the first cryptographic data in order to obtain second cryptographic data.