公开(公告)号：US11438154B2

公开(公告)日：2022-09-06

申请号：US16949013

申请日：2020-10-09

Applicant: Infineon Technologies AG

Inventor： Muhammad Hassan ,  Bernhard Rohfleisch ,  Alexander Zeh

IPC: H04L9/08 ,  H04L9/06 ,  G06F12/0888 ,  G06F12/14 ,  H04L9/14 ,  H04L9/32 ,  G06F21/60 ,  G06F12/0802

Abstract: A data cryptographic device may include a pre-tweak generator to generate pre-tweak values, a pre-tweak value cache memory to store one or more pre-tweak values generated by the pre-tweak generator, and a pre-tweak value selector to check whether a pre-tweak value for an input memory address is stored in the pre-tweak value cache memory. The data cryptographic device may further include a tweak generator to generate a tweak value based on the selected pre-tweak value, and a block cipher to perform at least one block cipher algorithm to at least one of encrypt data, encrypt and authenticate data, decrypt encrypted data, decrypt and verify encrypted and authenticated data, using a cryptographic key and the generated tweak value.

公开(公告)号：US20220326298A1

公开(公告)日：2022-10-13

申请号：US17713308

申请日：2022-04-05

Applicant: Infineon Technologies AG

Inventor： Muhammad Hassan ,  Jens Rosenbusch

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3177

Abstract: Testing of at least one source by a destination is provided, which comprises: (i) the destination supplies a test signal towards the at least one source; (ii) at the at least one source, determining a second output signal based on a first output signal and the test signal via a first function; (iii) conveying the second output signal to the destination; (iv) at the destination, determining a received signal based on the second output signal received from the at least one source and based on the test signal via a second function; and (v) determining whether an error occurred based on the received signal. Also, an according system is provided.

公开(公告)号：US11119695B2

公开(公告)日：2021-09-14

申请号：US16367694

申请日：2019-03-28

Applicant: Infineon Technologies AG

Inventor： Pedro Costa ,  Muhammad Hassan

IPC: G06F3/06 ,  G06F11/10 ,  G06F9/50 ,  G06F11/14 ,  G06F11/16 ,  G11C29/00 ,  G06F11/08 ,  G06F16/2455 ,  G06F9/38 ,  G06F12/0811

Abstract: A memory dispatcher, including an address decoder configured to decode a write address of received write data; a lockstep processor configured to generate, based on the decoded write address, primary and redundant memory write addresses and corresponding primary and redundant copies of the write data, if the decoded write address corresponds with a lockstep region of the memory; and a comparator coupled to the lockstep processor, and configured to compare the primary and redundant copies of the write data, and to compare the primary and redundant memory write addresses.

公开(公告)号：US10929949B2

公开(公告)日：2021-02-23

申请号：US16367635

申请日：2019-03-28

Applicant: Infineon Technologies AG

Inventor： Muhammad Hassan ,  Pedro Costa ,  Andre Roger ,  Romain Ygnace

IPC: G06T1/60 ,  G06F12/02 ,  G06T3/40

Abstract: A device for accessing memory configured to store an image data cube, wherein the memory has memory banks, and each memory bank has memory rows and memory columns. The device includes an input configured to receive a memory access request having a logical start address, which specifies a logical bank, a logical row, and a logical column, and a burst size; and a memory address generator configured to generate physical memory addresses based on the logical start address and the burst size, wherein any consecutive logical start addresses mapped to different memory rows are mapped to different memory banks.

公开(公告)号：US12196803B2

公开(公告)日：2025-01-14

申请号：US17713308

申请日：2022-04-05

Applicant: Infineon Technologies AG

Inventor： Muhammad Hassan ,  Jens Rosenbusch

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3177

Abstract: Testing of at least one source by a destination is provided, which comprises: (i) the destination supplies a test signal towards the at least one source; (ii) at the at least one source, determining a second output signal based on a first output signal and the test signal via a first function; (iii) conveying the second output signal to the destination; (iv) at the destination, determining a received signal based on the second output signal received from the at least one source and based on the test signal via a second function; and (v) determining whether an error occurred based on the received signal. Also, an according system is provided.

公开(公告)号：US20230128057A1

公开(公告)日：2023-04-27

申请号：US17965166

申请日：2022-10-13

Applicant: Infineon Technologies AG

Inventor： Muhammad Hassan ,  Konrad Walluszik ,  Juergen Schaefer

IPC: G06N3/063 ,  G06F7/544

Abstract: A system for executing an artificial neural network having a plurality of interconnected nodes, the system includes a memory storing weight values of the neural network. The memory can be configured to a store node value and a mask bit value for each of the plurality of nodes of the neural network. Further the system can include multiply and accumulate (MAC) units to perform operations for determining node values. The system includes a control unit circuitry that, during execution of the neural network, dynamically controls operations of the MAC units to cause a reduction in a number of calculations to be performed by the MAC units. The control unit circuitry causes the MAC units to perform operations involving a subset of the plurality of nodes to avoid performing operations involving nodes of the plurality nodes that are outside of the subset.

公开(公告)号：US20200311863A1

公开(公告)日：2020-10-01

申请号：US16367635

申请日：2019-03-28

Applicant: Infineon Technologies AG

Inventor： Muhammad Hassan ,  Pedro Costa ,  Andre Roger ,  Romain Ygnace

IPC: G06T1/60 ,  G06T3/40 ,  G06F12/02

Abstract: A device for accessing memory configured to store an image data cube, wherein the memory has memory banks, and each memory bank has memory rows and memory columns. The device includes an input configured to receive a memory access request having a logical start address, which specifies a logical bank, a logical row, and a logical column, and a burst size; and a memory address generator configured to generate physical memory addresses based on the logical start address and the burst size, wherein any consecutive logical start addresses mapped to different memory rows are mapped to different memory banks.

公开(公告)号：US12072699B2

公开(公告)日：2024-08-27

申请号：US17475361

申请日：2021-09-15

Applicant: Infineon Technologies AG

Inventor： Muhammad Hassan ,  Haram Kim ,  Taehoon Lee

IPC: G05B9/02 ,  G05B15/02 ,  G05B19/042

CPC classification number: G05B9/02 ,  G05B15/02 ,  G05B19/0425 ,  G05B2219/24003 ,  G05B2219/24146

Abstract: A microcontroller unit includes at least one core, a plurality of safety fault management units, with each safety fault management unit including circuitry to detect one or more safety faults and to output an alarm signal in response to detection of one or more safety faults. The microcontroller further includes system control units operating in parallel to the at least one core. Each of the plurality of system control units can be coupled to at least one of the safety fault management units and can include hardware circuitry to generate and output a port emergency stop (PES) signal based on the alarm signals obtained from a safety fault management unit. The microcontroller includes port circuitries coupled to ports and to the system control units. The port circuitries can selectively cause a respectively connected port to enter a non-operational electronic state in response to receiving a PES signal.

公开(公告)号：US20200310683A1

公开(公告)日：2020-10-01

申请号：US16367694

申请日：2019-03-28

Applicant: Infineon Technologies AG

Inventor： Pedro Costa ,  Muhammad Hassan

IPC: G06F3/06 ,  G06F11/10 ,  G06F9/50

Abstract: A memory dispatcher, including an address decoder configured to decode a write address of received write data; a lockstep processor configured to generate, based on the decoded write address, primary and redundant memory write addresses and corresponding primary and redundant copies of the write data, if the decoded write address corresponds with a lockstep region of the memory; and a comparator coupled to the lockstep processor, and configured to compare the primary and redundant copies of the write data, and to compare the primary and redundant memory write addresses.