公开(公告)号：US20190102182A1

公开(公告)日：2019-04-04

申请号：US15721458

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Venkateswara Madduri ,  Elmoustapha Ould-Ahmed-Vall ,  Jesus Corbal ,  Mark Charney ,  Robert Valentine ,  Binwei Yang

IPC: G06F9/30

Abstract: An apparatus and method for performing dual concurrent multiplications of packed data elements. For example one embodiment of a processor comprises: a decoder to decode a first instruction to generate a decoded instruction; a first source register to store a first plurality of packed data elements; a second source register to store a second plurality of packed data elements; execution circuitry to execute the decoded instruction, the execution circuitry comprising: multiplier circuitry to perform concurrent dual multiplications of a first packed data element from the first source register with a second packed data element from the second source register and a third packed data element from the first source register with a fourth packed data element from the second source register to generate first and second products, respectively, wherein the first and third packed data elements have a width twice as large as a width of the second and fourth packed data elements; the multiplier circuitry to select the first and third packed data elements from the first source register and the second and fourth packed data elements from the second source register in accordance with the immediate to generate the first and second products.

公开(公告)号：US10223114B1

公开(公告)日：2019-03-05

申请号：US15721602

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Venkateswara Madduri ,  Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Mark Charney

IPC: G06F9/30 ,  G06F7/483

Abstract: Embodiments of instructions and methods of execution of said instructions and resources to execute said instructions are detailed. For example, in an embodiment, a processor comprising: decode circuitry to decode an instruction having fields for an opcode, a packed data source operand identifier, and a packed data destination operand identifier; and execution circuitry to execute the decoded instruction to convert a data element from a least significant packed data element position of the identified packed data source operand from a fixed-point representation to a floating point representation, store the floating point representation into a 32-bit least significant packed data element position of the identified packed data destination operand, and zero all remaining packed data elements of the identified packed data destination operand is described.