公开(公告)号：US5208877A

公开(公告)日：1993-05-04

申请号：US751737

申请日：1991-08-29

申请人： Kent A. Murphy ,  Ashish Vengsarkar ,  Brian Fogg ,  Jonathan Greene ,  Richard O. Claus

发明人： Kent A. Murphy ,  Ashish Vengsarkar ,  Brian Fogg ,  Jonathan Greene ,  Richard O. Claus

IPC分类号： G01D5/353 ,  G02B6/14

CPC分类号： G02B6/02047 ,  G01D5/3538 ,  G02B6/02123 ,  G02B6/14

摘要： Two-mode, elliptical-core optic fibers with a permanent photo-induced index change are used as sensors with sensitivity varying as a function of length. The optic fiber sensors act as vibrational-mode filters thereby performing initial signal processing of the sensor signal. The sensors are based on photo-induced refractive index changes. These refractive index changes affect the differential phase modulation between the LP.sub.01 and the LP.sub.11.sup.even modes. The change in beat-length is dependent on the amount of strain induced in the fiber while the grating is being formed. The pattern is thus varied along the length of the fiber by straining the fiber in a specific fashion while the grating is being written. This changes the sensitivity, of the sensor along its length. By choosing an appropriate weighting function in the manufacture of the sensor, it is possible to implement vibrational-mode analysis, vibrational-mode filtering and other functions that are critical in control system applications.

摘要翻译： 使用具有永久光诱导指数变化的双模，椭圆芯光纤作为传感器，灵敏度随长度的变化而变化。 光纤传感器用作振动模式滤波器，从而执行传感器信号的初始信号处理。 传感器基于光诱导的折射率变化。 这些折射率变化影响LP01和LP11模式之间的差分相位调制。 拍子长度的变化取决于在形成光栅时光纤中诱发的应变量。 因此，通过在光栅被写入时以特定的方式使光纤变窄，沿着光纤的长度变化图案。 这会改变传感器沿其长度的灵敏度。 通过在传感器的制造中选择适当的加权函数，可以实现在控制系统应用中至关重要的振动模式分析，振动模式滤波和其他功能。

公开(公告)号：US09170774B2

公开(公告)日：2015-10-27

申请号：US13494850

申请日：2012-06-12

申请人： Volker Hecht ,  Marcel Derevlean ,  Jonathan Greene

发明人： Volker Hecht ,  Marcel Derevlean ,  Jonathan Greene

IPC分类号： G06F7/508

CPC分类号： G06F7/508

摘要： A fast lookahead carry adder includes adder logic and lookahead carry-path logic coupled to the adder logic. The carry path logic has a main carry path, a carry entrance path and a carry exit path, the carry entrance path separate from the carry exit path.

摘要翻译： 快速前瞻进位加法器包括耦合到加法器逻辑的加法器逻辑和先行进位逻辑逻辑。 进位路径逻辑具有主进位路径，进位入口路径和进位出口路径，进位路径与进位出口路径分离。

公开(公告)号：US08868820B2

公开(公告)日：2014-10-21

申请号：US13285210

申请日：2011-10-31

申请人： Volker Hecht ,  Jonathan Greene

发明人： Volker Hecht ,  Jonathan Greene

IPC分类号： G06F12/00 ,  H03K19/177

CPC分类号： G06F12/00 ,  H03K19/17768 ,  H03K19/17796

摘要： A random-access memory block for a field programmable gate array includes a random-access memory array having address inputs, a data input, a data output and including a plurality of storage locations. At least two programmably invertible enable inputs are provided. Hardwired decoding logic is coupled to the at least two programmably invertible enable inputs to selectively enable the random-access memory array. A gate is coupled to the output of the random-access memory array and is configured to pass the output of the random-access memory array only if the random-access memory is enabled for a read operation, and otherwise generate a preselected logic state.

摘要翻译： 用于现场可编程门阵列的随机存取存储器块包括具有地址输入，数据输入，数据输出并且包括多个存储位置的随机存取存储器阵列。 提供至少两个可编程的可逆可用输入。 硬连线解码逻辑被耦合到至少两个可编程的可逆可用使能输入以选择性地启用随机存取存储器阵列。 门被耦合到随机存取存储器阵列的输出，并且被配置为仅当对读操作启用随机存取存储器时才传递随机存取存储器阵列的输出，否则生成预选逻辑状态。

公开(公告)号：US08446170B2

公开(公告)日：2013-05-21

申请号：US13463232

申请日：2012-05-03

申请人： Joel Landry ,  Jonathan Greene ,  William C. Plants ,  Wenyi Feng

发明人： Joel Landry ,  Jonathan Greene ,  William C. Plants ,  Wenyi Feng

IPC分类号： H03K19/177

CPC分类号： H03K19/177 ,  G11C8/16 ,  H03K19/1776

摘要： A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array with logic modules and routing interconnects programmably coupleable to the logic modules and the RAM circuit. The RAM circuit has three ports: a first readable port, a second readable port, and a writeable port. The read ports may be programmably synchronous or asynchronous and have a programmably bypassable output pipeline register. The RAM circuit is especially well adapted for implementing register files. A novel interconnect method is also described.

摘要翻译： 公开了一种适用于现场可编程门阵列集成电路器件的随机存取存储器电路。 FPGA具有可编程阵列，其具有逻辑模块和路由互连，可编程地耦合到逻辑模块和RAM电路。 RAM电路具有三个端口：第一可读端口，第二可读端口和可写入端口。 读端口可以是可编程同步的或异步的，并且具有可编程可旁路输出流水线寄存器。 RAM电路特别适用于实现寄存器文件。 还描述了一种新颖的互连方法。

公开(公告)号：US20120259908A1

公开(公告)日：2012-10-11

申请号：US13494850

申请日：2012-06-12

申请人： Volker Hecht ,  Marcel Derevlean ,  Jonathan Greene

发明人： Volker Hecht ,  Marcel Derevlean ,  Jonathan Greene

IPC分类号： G06F7/508

CPC分类号： G06F7/508

摘要： A fast lookahead carry adder includes adder logic and lookahead carry-path logic coupled to the adder logic. The carry path logic has a main carry path, a carry entrance path and a carry exit path, the carry entrance path separate from the carry exit path.

摘要翻译： 快速前瞻进位加法器包括耦合到加法器逻辑的加法器逻辑和先行进位逻辑逻辑。 进位路径逻辑具有主进位路径，进位入口路径和进位出口路径，进位路径与进位出口路径分离。