公开(公告)号：US06723644B2

公开(公告)日：2004-04-20

申请号：US10094994

申请日：2002-03-12

申请人： Jung-yup Kim ,  Sang-rok Hah

发明人： Jung-yup Kim ,  Sang-rok Hah

IPC分类号： H01L2131

CPC分类号： H01L21/31053 ,  H01L21/31055

摘要： A method of manufacturing a semiconductor device is capable of preventing a dishing phenomenon from occurring without using dummy patterns. A plurality of conductive patterns are formed along the entire surface of a semiconductor substrate with an irregular pattern density. The conductive patterns have a first stopper layer at the top thereof. An interlayer insulating layer is formed on the conductive patterns. Next, a second stopper layer is formed on the interlayer insulating layer. An etching mask is formed on the second stopper layer so as to expose a first region having a conductive pattern density that is higher than that of another region(s). By using the etching mask, the second stopper layer and part of the interlayer insulating layer are etched at the first region. The resultant structure is then first polished to expose the first stopper layer at the first region, by using a slurry that provides a polishing rate for the interlayer insulating layer that is higher than that for either the first and second stopper layers. The resultant structure is then polished for a second time to remove the second stopper layer form the region(s) of lower pattern density, by using a slurry that provides a polishing rate that is higher for the second stopper layer than for either the first stopper layer and the interlayer insulating layer.

摘要翻译： 制造半导体器件的方法能够防止在不使用虚设图案的情况下发生凹陷现象。 沿着半导体衬底的整个表面以不规则图案密度形成多个导电图案。 导电图案在其顶部具有第一阻挡层。 在导电图案上形成层间绝缘层。 接着，在层间绝缘层上形成第二阻挡层。 在第二阻挡层上形成蚀刻掩模，以暴露具有高于另一区域的导电图案密度的第一区域。 通过使用蚀刻掩模，在第一区域处蚀刻第二阻挡层和层间绝缘层的一部分。 然后首先对所得到的结构进行抛光，以通过使层间绝缘层的抛光速率高于第一和第二阻挡层的抛光速率的浆料在第一区域露出第一阻挡层。 然后将所得到的结构第二次抛光，通过使用提供比第二塞子层更高的抛光速率的浆料，而不是第一塞子的抛光速率，从而形成具有较低图案密度的区域的第二塞子层 层和层间绝缘层。