公开(公告)号：US20240363505A1

公开(公告)日：2024-10-31

申请号：US18765477

申请日：2024-07-08

申请人： Taiwan Semicondutor Manufacturing Company, Ltd.

发明人： Feng-Wei KUO ,  Wen-Shiang Liao

IPC分类号： H01L23/495 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/768 ,  H01L23/00 ,  H01L23/29 ,  H01L23/498 ,  H01L23/522

CPC分类号： H01L23/49589 ,  H01L21/02422 ,  H01L21/31055 ,  H01L21/76832 ,  H01L23/29 ,  H01L23/49827 ,  H01L23/5223 ,  H01L24/05 ,  H01L24/11 ,  H01L28/40 ,  H01L28/60 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2924/19041

摘要： The present disclosure is directed to a method for forming metal insulator metal decoupling capacitors with scalable capacitance. The method can include forming a first redistribution layer with metal lines on a portion of a polymer layer, depositing a photoresist layer on the first redistribution layer, and etching the photoresist layer to form spaced apart first and second TIV openings in the photoresist layer, where the first TIV opening is wider than the second TIV opening. The method can further include depositing a metal in the first and second TIV openings to form respective first and second TIV structures in contact with the metal line, removing the photoresist layer, forming a high-k dielectric on a top surface of the first and second TIV structures, and depositing a metal layer on the high-k dielectric layer to form respective first and second capacitors.

公开(公告)号：US20240355695A1

公开(公告)日：2024-10-24

申请号：US18761906

申请日：2024-07-02

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Po-Shu WANG

IPC分类号： H01L23/31 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/768 ,  H01L23/29 ,  H01L23/535

CPC分类号： H01L23/3171 ,  H01L21/02131 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/31055 ,  H01L21/76805 ,  H01L21/76819 ,  H01L21/76895 ,  H01L23/291 ,  H01L23/3192 ,  H01L23/535

摘要： A semiconductor device includes: a protruding conductive structure that protrudes to a height from a first surface of the semiconductor device; and a first passivation layer, the first passivation layer overlaying the protruding conductive structure by a first thickness, the first passivation layer overlaying the first surface by a second thickness greater than the first thickness, wherein the first passivation layer is planar at a top surface over the first thickness and the second thickness.

公开(公告)号：US12062563B2

公开(公告)日：2024-08-13

申请号：US17881508

申请日：2022-08-04

申请人： EBARA CORPORATION

发明人： Itsuki Kobata ,  Keita Yagi ,  Katsuhide Watanabe ,  Yoichi Shiokawa ,  Toru Maruyama ,  Nobuyuki Takahashi

IPC分类号： H01L21/677 ,  B24B37/04 ,  B24B37/20 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/66 ,  H01L21/67 ,  H01L21/683

CPC分类号： H01L21/67742 ,  B24B37/04 ,  B24B37/20 ,  H01L21/30612 ,  H01L21/30625 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/32115 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/6708 ,  H01L21/67092 ,  H01L21/67248 ,  H01L21/67253 ,  H01L21/6838 ,  H01L22/26 ,  H01L22/12

摘要： An object of the present invention is to improve a substrate processing apparatus using the CARE method. The present invention provides a substrate processing apparatus for polishing a processing target region of a substrate by bringing the substrate and a catalyst into contact with each other in the presence of processing liquid. The substrate processing apparatus includes a substrate holding unit configured to hold the substrate, a catalyst holding unit configured to hold the catalyst, and a driving unit configured to move the substrate holding unit and the catalyst holding unit relative to each other with the processing target region of the substrate and the catalyst kept in contact with each other. The catalyst is smaller than the substrate.

公开(公告)号：US20240213034A1

公开(公告)日：2024-06-27

申请号：US18601433

申请日：2024-03-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Ming Chang ,  Chih-Ming Lai ,  Chung-Ju Lee ,  Ru-Gun Liu ,  Shau-Lin Shue ,  Tien-I Bao ,  Tsai-Sheng Gau

IPC分类号： H01L21/321 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L21/3212 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L21/76834 ,  H01L21/76883 ,  H01L2221/1063

摘要： An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on the first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.

公开(公告)号：US20240188307A1

公开(公告)日：2024-06-06

申请号：US18441204

申请日：2024-02-14

申请人： Kioxia Corporation

发明人： Masahiro KIYOTOSHI ,  Akihito YAMAMOTO ,  Yoshio OZAWA ,  Fumitaka ARAI ,  Riichiro SHIROTA

IPC分类号： H10B63/00 ,  H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/762 ,  H01L27/105 ,  H01L29/51 ,  H10B43/27 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40 ,  H10B69/00 ,  H10B99/00 ,  H10N70/00 ,  H10N70/20

CPC分类号： H10B63/845 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/30604 ,  H01L21/31055 ,  H01L21/3212 ,  H01L21/32136 ,  H01L21/762 ,  H01L27/105 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/518 ,  H10B43/27 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40 ,  H10B63/00 ,  H10B63/20 ,  H10B63/30 ,  H10B69/00 ,  H10B99/00 ,  H10N70/021 ,  H10N70/231 ,  H10N70/801 ,  H10N70/882 ,  H10N70/028 ,  H10N70/20 ,  H10N70/823 ,  H10N70/8413 ,  H10N70/8828 ,  H10N70/8833

摘要： A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.

公开(公告)号：US11955371B2

公开(公告)日：2024-04-09

申请号：US17444669

申请日：2021-08-08

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Jingwen Lu ,  Hai-Han Hung ,  Meng-Cheng Chen

IPC分类号： H01L21/762 ,  H01L21/3105 ,  H01L21/768

CPC分类号： H01L21/76224 ,  H01L21/31055 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76897

摘要： A method for preparing a semiconductor device includes: providing a semiconductor substrate, in which a trench is formed on the semiconductor substrate, a filling layer is formed in the trench, and a void is formed in the filling layer; removing a portion of the filling layer to expose the void; forming a plug, in which the plug is configured to plug the void and extends into the void by at least a preset distance; and removing a portion of the filling layer and remaining the plug with at least a preset height until the filling layer reaches a preset thickness to form a contact hole.

公开(公告)号：US11929258B2

公开(公告)日：2024-03-12

申请号：US17397756

申请日：2021-08-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Ming Chang ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Tsai-Sheng Gau ,  Chung-Ju Lee ,  Tien-I Bao ,  Shau-Lin Shue

IPC分类号： H01L21/321 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L21/3212 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L21/76834 ,  H01L21/76883 ,  H01L2221/1063

摘要： An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.

公开(公告)号：US20230290641A1

公开(公告)日：2023-09-14

申请号：US18319454

申请日：2023-05-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： CHUN-HUNG LIAO ,  CHUNG-WEI HSU ,  TSUNG-LING TSAI ,  CHEN-HAO WU ,  AN-HSUAN LEE ,  SHEN-NAN LEE ,  TENG-CHUN TSAI ,  HUANG-LIN CHAO

IPC分类号： H01L21/3105 ,  C09K3/14 ,  H01L21/306 ,  C09G1/02 ,  H01L21/3063 ,  H01L21/311 ,  H01L21/02 ,  C23F1/12

CPC分类号： H01L21/31053 ,  C09K3/1409 ,  H01L21/30625 ,  C09G1/02 ,  H01L21/3063 ,  H01L21/31111 ,  H01L21/02019 ,  C23F1/12 ,  H01L21/31055

摘要： The present disclosure provides a method for manufacturing a semiconductor. The method includes: forming a metal oxide layer over a gate structure over a substrate; forming a dielectric layer over the metal oxide layer; forming a metal layer over the metal oxide layer; and performing a chemical mechanical polish (CMP) operation to remove a portion of the dielectric layer and a portion of the metal layer, the CMP operation stopping at the metal oxide layer, wherein a slurry used in the CMP operation includes a ceria compound. The present disclosure also provides a method for planarizing a metal-dielectric surface.

公开(公告)号：US20230268427A1

公开(公告)日：2023-08-24

申请号：US18306769

申请日：2023-04-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsu Ming Hsiao ,  Ming-Jhe Sie ,  Hsiu-Hao Tsao ,  Hong Pin Lin ,  Che-fu Chen ,  An Chyi Wei ,  Yi-Jen Chen

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L21/3105

CPC分类号： H01L29/6681 ,  H01L21/823431 ,  H01L21/31055 ,  H01L21/823468 ,  H01L21/823418 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656

摘要： A method, for making a semiconductor device, includes forming a first fin over a substrate. The method includes forming a dummy gate stack on the first fin. The method includes forming a first gate spacer along a side of the dummy gate stack. The first gate spacer includes a first dielectric material. The method includes forming a second gate spacer along a side of the first gate spacer. The second gate spacer includes a semiconductor material. The method includes forming a source/drain region in the first fin adjacent the second gate spacer. The method includes removing at least a portion of the second gate spacer to form a void extending between the first gate spacer and the source/drain region.

公开(公告)号：US20230207394A1

公开(公告)日：2023-06-29

申请号：US18111079

申请日：2023-02-17

申请人： KEY FOUNDRY CO., LTD.

发明人： Yang Beom KANG ,  Kang Sup SHIN

IPC分类号： H01L21/8234 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L21/285 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/764 ,  H01L21/762 ,  H01L21/8236 ,  H01L29/66 ,  H01L29/45 ,  H01L27/088

CPC分类号： H01L21/823481 ,  H01L29/7816 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/1083 ,  H01L21/28518 ,  H01L21/26513 ,  H01L21/31055 ,  H01L21/02129 ,  H01L21/764 ,  H01L21/76237 ,  H01L21/823493 ,  H01L21/8236 ,  H01L29/66681 ,  H01L29/45 ,  H01L27/0883

摘要： A semiconductor device includes etch stop films formed on the first gate electrode, the first source region, the first drain region, and the shallow trench isolation regions, respectively. First interlayer insulating films are formed on the etch stop film, respectively. Deep trenches are formed in the substrate between adjacent ones of the first interlayer insulating films to overlap the shallow trench isolation regions. Sidewall insulating films are formed in the deep trenches, respectively. A gap-fill insulating film is formed on the sidewall insulating film. A second interlayer insulating film is formed on the gap-fill insulating film. A top surface of the second interlayer insulating film is substantially planar and a bottom surface of the second interlayer insulating film is undulating.