公开(公告)号：US07688925B2

公开(公告)日：2010-03-30

申请号：US11195082

申请日：2005-08-01

申请人： Edward Lee ,  Arvind Bomdica ,  Lin Chen ,  Claude Gauthier ,  Sam Huynh ,  Hiok-Tiaq Ng ,  John Ling ,  Jennifer Ho ,  Siji Menokki Kandiyil ,  Gin Yee ,  Joseph Macri

发明人： Edward Lee ,  Arvind Bomdica ,  Lin Chen ,  Claude Gauthier ,  Sam Huynh ,  Hiok-Tiaq Ng ,  John Ling ,  Jennifer Ho ,  Siji Menokki Kandiyil ,  Gin Yee ,  Joseph Macri

IPC分类号： H04L7/00

CPC分类号： H03L7/0814 ,  H03L7/07 ,  H03L7/0805 ,  H04L7/0004 ,  H04L7/0037 ,  H04L7/0337

摘要： An IO method and system for bit-deskewing are described. Embodiment includes a computer system with multiple components that transfer data among them. In one embodiment, a system component receives a forward strobe signal and multiple data bit signals from a transmitting component. The receiving component includes a forward strobe clock recovery circuit configurable to align a forward strobe sampling clock so as to improve sampling accuracy. The receiving component further includes at least one data bit clock recovery circuit configurable to align a data bit sampling clock so as to improve sampling accuracy, and to receive a signal from the forward strobe clock recovery circuit that causes the data bit sampling clock to track the forward strobe sampling clock during system operation.

摘要翻译： 描述了用于位移校正的IO方法和系统。 实施例包括具有在其间传送数据的多个组件的计算机系统。 在一个实施例中，系统组件从发送组件接收正向选通信号和多个数据位信号。 接收组件包括可选择对准前向选通采样时钟以提高采样精度的正向选通时钟恢复电路。 接收组件还包括至少一个数据比特时钟恢复电路，可配置为对准数据比特采样时钟，以提高采样精度，并接收来自正向选通时钟恢复电路的信号，使得数据比特采样时钟跟踪 系统运行期间的正向选通采样时钟。

公开(公告)号：US20080157817A1

公开(公告)日：2008-07-03

申请号：US12046887

申请日：2008-03-12

申请人： Oleg Drapkin ,  Grigori Temkine ,  Arvind Bomdica ,  Kevin Liang

发明人： Oleg Drapkin ,  Grigori Temkine ,  Arvind Bomdica ,  Kevin Liang

IPC分类号： H03K19/0185

CPC分类号： H03K19/0185 ,  H03K19/094

摘要： An input signal is routed to a first logic one reference signal generator or alternatively routed to a second logic one reference signal generator based at least one a voltage level of the input signal. When the voltage level of the input signal is less than a threshold value, the first logic one reference signal generator selectively generates a first logic one reference signal. When the voltage level of the input signal is greater than or equal to the threshold value, the second logic one reference signal generator alternatively generates a second logic one reference signal. The first and second logic one reference signals may be used to control a first voltage scaling circuit that drives a scaled output signal having a logic one value corresponding to the voltage level of the first logic one reference signal.

摘要翻译： 输入信号被路由到第一逻辑一个参考信号发生器，或者基于输入信号的至少一个电压电平路由到第二逻辑1参考信号发生器。 当输入信号的电压电平小于阈值时，第一逻辑1参考信号发生器选择性地产生第一逻辑1参考信号。 当输入信号的电压电平大于或等于阈值时，第二逻辑1参考信号发生器交替产生第二逻辑1参考信号。 第一和第二逻辑一个参考信号可以用于控制驱动具有对应于第一逻辑1参考信号的电压电平的逻辑1值的定标输出信号的第一电压缩放电路。

公开(公告)号：US20110063010A1

公开(公告)日：2011-03-17

申请号：US12560991

申请日：2009-09-16

申请人： Jinyung Namkoong ,  Arvind Bomdica ,  Ming-Ju Lee

发明人： Jinyung Namkoong ,  Arvind Bomdica ,  Ming-Ju Lee

IPC分类号： H03L5/00

CPC分类号： H03K19/018528

摘要： A circuit includes a differential circuit having at least to two inputs, a first variable impedance circuit, and a second variable impedance circuit. The first variable impedance circuit is between a first branch of the differential circuit and an output. The first variable impedance circuit provides a first variable impedance. The a second variable impedance circuit is between a second branch of the differential circuit and the output. The second variable impedance circuit provides a second variable impedance. The first variable impedance and the second variable impedance vary in accordance with a voltage difference between the two inputs.

摘要翻译： 电路包括具有至少两个输入的差分电路，第一可变阻抗电路和第二可变阻抗电路。 第一可变阻抗电路在差分电路的第一分支和输出之间。 第一可变阻抗电路提供第一可变阻抗。 第二可变阻抗电路在差分电路的第二分支和输出之间。 第二可变阻抗电路提供第二可变阻抗。 第一可变阻抗和第二可变阻抗根据两个输入之间的电压差而变化。

公开(公告)号：US07714615B2

公开(公告)日：2010-05-11

申请号：US12032741

申请日：2008-02-18

申请人： Yikai Liang ,  Arvind Bomdica ,  Min Xu ,  Ming-Ju Lee

发明人： Yikai Liang ,  Arvind Bomdica ,  Min Xu ,  Ming-Ju Lee

IPC分类号： H03K19/094

CPC分类号： H03K19/0019 ,  H04L1/08 ,  H04L25/0272 ,  H04L25/0286

摘要： A circuit for de-emphasizing information transmitted via a differential communication link includes a voltage mode differential circuit and a bi-directional current source circuit. The voltage mode differential circuit includes a first and second output terminal. The voltage mode differential circuit provides a first voltage via the first output terminal and second voltage via the second output terminal in response to a differential input voltage. The bi-directional current source circuit is operatively coupled between the first and second terminals. The bi-directional current source circuit selectively provides current in a first and second direction between the first and second terminals based on the first and second voltage.

摘要翻译： 用于去强调通过差分通信链路发送的信息的电路包括电压模式差分电路和双向电流源电路。 电压模式差分电路包括第一和第二输出端子。 电压模式差分电路响应于差分输入电压经由第一输出端经第二输出端提供第一电压和第二电压。 双向电流源电路可操作地耦合在第一和第二端子之间。 双向电流源电路基于第一和第二电压选择性地在第一和第二端子之间的第一和第二方向上提供电流。

公开(公告)号：US07999595B2

公开(公告)日：2011-08-16

申请号：US12560991

申请日：2009-09-16

申请人： Jinyung Namkoong ,  Arvind Bomdica ,  Ming-Ju Lee

发明人： Jinyung Namkoong ,  Arvind Bomdica ,  Ming-Ju Lee

IPC分类号： G03L5/00

CPC分类号： H03K19/018528

摘要： A circuit includes a differential circuit having at least to two inputs, a first variable impedance circuit, and a second variable impedance circuit. The first variable impedance circuit is between a first branch of the differential circuit and an output. The first variable impedance circuit provides a first variable impedance. The a second variable impedance circuit is between a second branch of the differential circuit and the output. The second variable impedance circuit provides a second variable impedance. The first variable impedance and the second variable impedance vary in accordance with a voltage difference between the two inputs.

摘要翻译： 电路包括具有至少两个输入的差分电路，第一可变阻抗电路和第二可变阻抗电路。 第一可变阻抗电路在差分电路的第一分支和输出之间。 第一可变阻抗电路提供第一可变阻抗。 第二可变阻抗电路在差分电路的第二分支和输出之间。 第二可变阻抗电路提供第二可变阻抗。 第一可变阻抗和第二可变阻抗根据两个输入之间的电压差而变化。

公开(公告)号：US07710150B2

公开(公告)日：2010-05-04

申请号：US12046887

申请日：2008-03-12

申请人： Oleg Drapkin ,  Grigori Temkine ,  Arvind Bomdica ,  Kevin Liang

发明人： Oleg Drapkin ,  Grigori Temkine ,  Arvind Bomdica ,  Kevin Liang

IPC分类号： H03K19/0175

CPC分类号： H03K19/0185 ,  H03K19/094

摘要： An input signal is routed to a first logic one reference signal generator or alternatively routed to a second logic one reference signal generator based at least one a voltage level of the input signal. When the voltage level of the input signal is less than a threshold value, the first logic one reference signal generator selectively generates a first logic one reference signal. When the voltage level of the input signal is greater than or equal to the threshold value, the second logic one reference signal generator alternatively generates a second logic one reference signal. The first and second logic one reference signals may be used to control a first voltage scaling circuit that drives a scaled output signal having a logic one value corresponding to the voltage level of the first logic one reference signal.

摘要翻译： 输入信号被路由到第一逻辑一个参考信号发生器，或者基于输入信号的至少一个电压电平路由到第二逻辑1参考信号发生器。 当输入信号的电压电平小于阈值时，第一逻辑1参考信号发生器选择性地产生第一逻辑1参考信号。 当输入信号的电压电平大于或等于阈值时，第二逻辑1参考信号发生器交替产生第二逻辑1参考信号。 第一和第二逻辑一个参考信号可以用于控制驱动具有对应于第一逻辑1参考信号的电压电平的逻辑1值的定标输出信号的第一电压缩放电路。

公开(公告)号：US07345510B1

公开(公告)日：2008-03-18

申请号：US11469311

申请日：2006-08-31

申请人： Oleg Drapkin ,  Grigori Temkine ,  Arvind Bomdica ,  Kevin Liang

发明人： Oleg Drapkin ,  Grigori Temkine ,  Arvind Bomdica ,  Kevin Liang

IPC分类号： H03K19/0175

CPC分类号： H03K19/0185 ,  H03K19/094

摘要： An input signal is routed to a first logic one reference signal generator or alternatively routed to a second logic one reference signal generator based at least one a voltage level of the input signal. When the voltage level of the input signal is less than a threshold value, the first logic one reference signal generator selectively generates a first logic one reference signal. When the voltage level of the input signal is greater than or equal to the threshold value, the second logic one reference signal generator alternatively generates a second logic one reference signal. The first and second logic one reference signals may be used to control a first voltage scaling circuit that drives a scaled output signal having a logic one value corresponding to the voltage level of the first logic one reference signal.

摘要翻译： 输入信号被路由到第一逻辑一个参考信号发生器，或者基于输入信号的至少一个电压电平路由到第二逻辑1参考信号发生器。 当输入信号的电压电平小于阈值时，第一逻辑1参考信号发生器选择性地产生第一逻辑1参考信号。 当输入信号的电压电平大于或等于阈值时，第二逻辑1参考信号发生器交替产生第二逻辑1参考信号。 第一和第二逻辑一个参考信号可以用于控制驱动具有对应于第一逻辑1参考信号的电压电平的逻辑1值的定标输出信号的第一电压缩放电路。