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    PASSIVE PHASE INTERPOLATOR
    1.
    发明公开
    PASSIVE PHASE INTERPOLATOR 审中-公开

    公开(公告)号：US20240364493A1

    公开(公告)日：2024-10-31

    申请号：US18141189

    申请日：2023-04-28

    Applicant: Analog Devices, Inc.

    Inventor： Narendra M.K. Rao ,  Rajasekhar Nagulapalli

    IPC: H04L7/00 ,  H04L7/033

    CPC classification number: H04L7/0025 ,  H04L7/0087 ,  H04L7/0337

    Abstract: A phase interpolator for generating a phase interpolated output signal between two phase separated input signals received at two phase separated input signal nodes may include a plurality of circuit elements. The plurality of circuit elements may include at least one of resistors or capacitors, in a series arrangement between the two phase separated input signal nodes, where respective connection points between respective ones of the plurality of circuit elements may provide at least one intermediate phase interpolated signal. The phase interpolator may also include selection circuitry, which may be configured to select the phase interpolated output signal from the at least one intermediate phase interpolated signal.

    REDUCING EYE ASYMMETRY CAUSED BY VOLTAGE VARIATION IN A CLOCK AND DATA RECOVERY CIRCUIT OR DELAY LOCKED LOOP
    2.
    发明公开
    REDUCING EYE ASYMMETRY CAUSED BY VOLTAGE VARIATION IN A CLOCK AND DATA RECOVERY CIRCUIT OR DELAY LOCKED LOOP 审中-公开

    公开(公告)号：US20240121073A1

    公开(公告)日：2024-04-11

    申请号：US17963970

    申请日：2022-10-11

    Applicant: QUALCOMM Incorporated

    Inventor： Jianwen YE ,  Julian PUSCAR

    IPC: H04L7/033 ,  H03L7/08 ,  H03L7/081 ,  H04L7/00

    CPC classification number: H04L7/0337 ,  H03L7/0807 ,  H03L7/0812 ,  H04L7/0025

    Abstract: A data communication interface has a delay-locked loop configured to generate a receive clock signal based on timing information provided by a signal received over a clock channel of a data communication link, a phase interpolator configured to provide a phase-shifted clock signal by phase-shifting one or more edges in the receive clock signal based on timing of transitions in a data signal received over a data channel of the data communication link, a clock and data recovery circuit configured to capture data from the data signal using the phase-shifted clock signal, and a calibration circuit. The calibration circuit is configured to calibrate the delay-locked loop while the clock and data recovery circuit is in an idle state, recalibrate the delay-locked loop when the clock and data recovery circuit is activated, and calibrate the clock and data recovery circuit after recalibrating the delay-locked loop.

    PHASE CALIBRATION OF CLOCK SIGNALS
    5.
    发明申请
    PHASE CALIBRATION OF CLOCK SIGNALS 审中-公开

    公开(公告)号：US20190173661A1

    公开(公告)日：2019-06-06

    申请号：US16156868

    申请日：2018-10-10

    Applicant: Rambus Inc.

    Inventor： Marko Aleksic ,  Simon Li ,  Roxanne Vu

    IPC: H04L7/033 ,  H03L7/081 ,  H04L25/03 ,  H04L7/00

    CPC classification number: H04L7/033 ,  H03L7/081 ,  H04L7/0004 ,  H04L7/0079 ,  H04L7/0337 ,  H04L25/0292 ,  H04L25/03 ,  H04L25/03057 ,  H04L2025/03802

    Abstract: A receiver with clock phase calibration. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path.

    DEVICE AND METHOD FOR RECOVERING CLOCK AND DATA
    7.
    发明申请
    DEVICE AND METHOD FOR RECOVERING CLOCK AND DATA 审中-公开

    公开(公告)号：US20180323956A1

    公开(公告)日：2018-11-08

    申请号：US15585164

    申请日：2017-05-03

    Applicant: GLOBAL UNICHIP CORPORATION ,  TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Yen-Chung CHEN ,  Wen-Juh KANG ,  Cheng-Hung WU

    IPC: H04L7/033 ,  H04L7/00

    CPC classification number: H04L7/0331 ,  H03L7/0807 ,  H03L7/093 ,  H04L7/0025 ,  H04L7/0337

    Abstract: A clock and data recovery device includes a data analysis circuit, a loop filter circuit, and a phase adjust circuit. The data analysis circuit is configured to generate an error signal according to input data, a first clock signal, and a second clock signal. The loop filter circuit is configured to generate an adjust signal according to the error signal. A phase filter circuit is configured to generate a first control signal according to the error signal. A switching element of a first frequency filter circuit is configured to output a second control signal according to the error signal and a first switching signal that has a first period. A first adder is configured to generate the adjust signal according to the first control signal and the second control signal. The phase adjust circuit is configured to adjust the first clock signal and the second clock signal.

    Injection-locked phase interpolator
    8.
    发明授权
    Injection-locked phase interpolator 有权

    公开(公告)号：US10014868B1

    公开(公告)日：2018-07-03

    申请号：US15476861

    申请日：2017-03-31

    Applicant: Xilinx, Inc.

    Inventor： Mayank Raj

    IPC: H03L7/099 ,  H03B27/00

    CPC classification number: H03L7/24 ,  H04L7/0025 ,  H04L7/033 ,  H04L7/0337

    Abstract: An example phase interpolator includes: a ring oscillator having a plurality of delay stages and a plurality of injection switches, each of the plurality of injection switches responsive to a differential reference clock signal and a first differential control signal; a supply control circuit configured to provide a regulated supply voltage to the ring oscillator in response to a first component of a second differential control signal; and a ground control circuit configured to provide a regulated ground voltage to the ring oscillator in response to a second component of the second differential control signal.

    COLLABORATIVE CLOCK AND DATA RECOVERY
    10.
    发明申请
    COLLABORATIVE CLOCK AND DATA RECOVERY 审中-公开

    公开(公告)号：US20180152284A1

    公开(公告)日：2018-05-31

    申请号：US15799016

    申请日：2017-10-31

    Applicant: Rambus Inc.

    Inventor： Masum Hossain ,  Nhat Nguyen ,  Yikui Jen Dong ,  Arash Zargaran-Yazd

    IPC: H04L7/00 ,  H04L25/49 ,  H03K7/02 ,  H03L7/00

    CPC classification number: H04L7/0087 ,  H03K7/02 ,  H03L7/00 ,  H04L7/0025 ,  H04L7/0337 ,  H04L25/4917

    Abstract: A receiver serial data streams generates a local timing reference clock from an approximate frequency reference clock by phase-aligning the local clock to transitions in the data stream. This process is commonly known as clock and data recovery (CDR). Certain transitions of the data signals are selected for use in phase-aligning the local clock, and certain transitions are ignored. Phase-error signals from multiple receivers receiving the multiple serial data streams are combined and used to make common phase adjustments to the frequency reference clock. These common adjustments track jitter that is common to the received data streams. Local adjustments that better align each respective local clock to the transitions of its respective serial data stream are made using a local phase-error signal. These local adjustments track jitter that is more unique to each of the respective serial data streams.

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