公开(公告)号：US4558434A

公开(公告)日：1985-12-10

申请号：US573641

申请日：1984-01-25

申请人： Fumio Baba ,  Hirohiko Mochizuki ,  Hatsuo Miyahara

发明人： Fumio Baba ,  Hirohiko Mochizuki ,  Hatsuo Miyahara

IPC分类号： B26F1/32 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/40

CPC分类号： G11C11/4096 ,  G11C7/1006

摘要： A semiconductor memory device having matrix-arranged memory cells, carrying out data write or read operations to or from a selected memory cell through a pair of data buses by the selection of a word line and a pair of bit lines, includes two transfer devices which transfer data between bit lines and data buses and which are separately operated for either writing or reading. Even if a data read operation is stopped midway by a system reset or the like, the stored data in the memory cell is not destroyed.

摘要翻译： 具有矩阵排列的存储单元的半导体存储器件通过选择一条字线和一对位线，通过一对数据总线对所选存储单元执行数据写入或读操作，包括两个传输器件 在位线和数据总线之间传输数据，并分别操作写入或读取。 即使数据读取操作在系统复位等中途停止，存储单元中存储的数据也不会被破坏。