公开(公告)号：US5068829A

公开(公告)日：1991-11-26

申请号：US570525

申请日：1990-08-21

申请人： Yasunori Yamaguchi ,  Jun Miyake

发明人： Yasunori Yamaguchi ,  Jun Miyake

IPC分类号： G11C7/00 ,  G11C7/10 ,  H04N5/907

CPC分类号： H04N5/907 ,  G11C7/00 ,  G11C7/1006

摘要： A semiconductor memory device is provided with a memory portion, a logical operation circuit which receives the data signal read out from such memory portion and the input data signal to form data to be offered to such memory portion, and a gate circuit. In case a data input operation is required which eliminates the logical operation, the input data signal is fed not via the long logical operation circuit, but via the gate circuit directly to the memory portion. The semiconductor memory device constructed as above permits a high speed operation and is suited for use as the memory for image processing.

摘要翻译： 半导体存储器件具有存储器部分，逻辑运算电路，其接收从这种存储器部分读出的数据信号和输入数据信号，以形成要提供给这种存储器部分的数据;以及门电路。 在需要消除逻辑运算的数据输入操作的情况下，输入数据信号不经由长逻辑运算电路馈送，而是经由门电路直接馈送到存储器部分。 如上构造的半导体存储器件允许高速操作，并且适合用作用于图像处理的存储器。

公开(公告)号：US4933900A

公开(公告)日：1990-06-12

申请号：US281964

申请日：1988-11-30

申请人： Yasunori Yamaguchi ,  Jun Miyake

发明人： Yasunori Yamaguchi ,  Jun Miyake

IPC分类号： G06F12/00 ,  G06F12/04 ,  G06F12/06 ,  G11C7/00 ,  G11C11/401 ,  G11C11/4096

CPC分类号： G11C11/4096

摘要： A single chip semiconductor memory device having an arithmetic circuit to conduct plural kinds of arithmetic operations and a mask control circuit for inhibiting a substantial change in data in memory irrespective of the operations of the arithmetic circuit when it is brought into a masking state. The semiconductor memory device takes a preset operation mode for receiving from the outside a control signal for the arithmetic circuit and the mask control circuit. This control signal for the arithmetic circuit and the mask control circuit, which is given to the semiconductor memory device when in the preset operation mode, is latched in the semiconductor memory device until the device is brought again into the preset operation mode.

摘要翻译： 具有用于进行多种算术运算的算术电路的单芯片半导体存储器件和用于在与运算电路进入掩蔽状态时的操作无关地抑制存储器中的数据的实质变化的掩码控制电路。 半导体存储器件采用预设的操作模式，用于从外部接收用于运算电路和掩模控制电路的控制信号。 当处于预设操作模式时给予半导体存储器件的运算电路和掩模控制电路的该控制信号被锁存在半导体存储器件中，直到器件再次进入预置操作模式。