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公开(公告)号:US07047365B2
公开(公告)日:2006-05-16
申请号:US10054042
申请日:2002-01-22
IPC分类号: G06F12/00
CPC分类号: G06F9/30043 , G06F12/0831 , G06F12/0837 , G06F2212/507
摘要: A method and apparatus for purging a cache line from an issuing processor and sending the cache line to the cache of one or more processors in a multi-processor shared memory computer system. The method and apparatus enables cache line data to be moved from one processor to another before the receiving processor needs the data thus preventing the receiving processor from incurring a cache miss event.