公开(公告)号：US20230056500A1

公开(公告)日：2023-02-23

申请号：US17405457

申请日：2021-08-18

Applicant: Micron Technology, Inc.

Inventor： Patrick Estep ,  Tony M. Brewer

IPC: G06F9/52 ,  G06F9/50

Abstract: Devices and techniques for CHAINED RESOURCE LOCKING are described herein. Threads form a last-in-first-out (LIFO) queue on a resource lock to create a chained lock on the resource. A data store representing the lock for the resource holds the previous thread’s identifier, enabling a subsequent thread to wake the previous thread using the identifier when the subsequent thread releases the lock. Generally, the thread releasing the lock need not interact with the data store, reducing contention for the data store among many threads.

公开(公告)号：US11550642B1

公开(公告)日：2023-01-10

申请号：US17405233

申请日：2021-08-18

Applicant: Micron Technology, Inc.

Inventor： Patrick Estep ,  Skyler Arron Windh ,  Tony M. Brewer

IPC: G06F9/54 ,  G06F9/30

Abstract: Devices and techniques for triggering early termination of cooperating processes in a processor are described herein. A system includes multiple memory-compute nodes, wherein a memory-compute node comprises: event manager circuitry configured to establish a broadcast channel to receive event messages; and thread manager circuitry configured to organize a plurality of threads to perform portions of a cooperative task, wherein the plurality of threads each monitor the broadcast channel to receive event messages on the broadcast channel, and wherein upon achieving a threshold operation, the thread manager circuitry is to use the event manager circuitry to broadcast, on the broadcast channel, an event message indicating that the cooperative task is complete, causing other threads, in response to receiving the event message, to terminate execution of their respective portions of the cooperative task.

公开(公告)号：US20220317972A1

公开(公告)日：2022-10-06

申请号：US17405368

申请日：2021-08-18

Applicant: Micron Technology, Inc.

Inventor： Douglas Vanesko ,  Tony M. Brewer ,  Bryan Hornung ,  Patrick Estep

IPC: G06F7/548

Abstract: Devices and techniques for hardware for concurrent SINE and cosine determination are described herein. A first sequence of bits representing an angle of a line from an origin to a unit circle can be obtained. A quadrant of the unit circle for the line is determined and the two least significant bits of the first sequence of bits is replaced with an encoding for the quadrant, the angle is translated to a base quadrant angle and sin and cosine operations are performed on a portion of a second sequence of bits (derived from the first sequence of bits) to create intermediate sin and cosine solutions in the base quadrant. The quadrant encoding in the first sequence of bits is then used to create a final sin and cosine solutions in the quadrant from the intermediate solutions.