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公开(公告)号：US12242884B2
公开(公告)日：2025-03-04
申请号：US17402849
申请日：2021-08-16
Applicant: Micron Technology, Inc.
Inventor： Douglas Vanesko , Bryan Hornung
Abstract: Various examples are directed to systems and methods for performing operations in a reconfigurable compute fabric. A dispatch interface may send a first asynchronous message to a first flow controller of a first synchronous flow. The first asynchronous message may instruct the first flow controller to begin execution of a first-level loop. The first synchronous flow may send a second asynchronous message to a second flow controller of a second synchronous flow. The second asynchronous message may instruct the second flow controller to execute a second-level loop. The first flow controller may receive a third asynchronous message indicating that the second-level loop has completed and that a synchronous flow thread is free for executing a next iteration of the first-level loop.
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公开(公告)号：US11861366B2
公开(公告)日：2024-01-02
申请号：US17399801
申请日：2021-08-11
Applicant: Micron Technology, Inc.
Inventor： Douglas Vanesko , Tony M. Brewer
CPC classification number: G06F9/325 , G06F9/3867
Abstract: Disclosed in some examples, are methods, systems, devices, and machine-readable mediums which provide for more efficient CGRA execution by assigning different initiation intervals to different PEs executing a same code base. The initiation intervals may be a multiple of each other and the PE with the lowest initiation interval may be used to execute instructions of the code that is to be executed at a greater frequency than other instructions than other instructions that may be assigned to PEs with higher initiation intervals.
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公开(公告)号：US20240330237A1
公开(公告)日：2024-10-03
申请号：US18743637
申请日：2024-06-14
Applicant: Micron Technology, Inc.
Inventor： Bryan Hornung , Douglas Vanesko , Divid Patrick
CPC classification number: G06F15/80 , G06F9/30018 , G06F15/7867
Abstract: Devices and techniques for loading contexts in a coarse-grained reconfigurable array processor are described herein. A system or apparatus may include context load circuitry operable to load context for a coarse-grained reconfigurable array processor, where the context load circuitry is configured to: (a) receive a kernel identifier; (b) access a first registry to obtain a context mask base address; (c) determine a context mask address from the context mask base address and the kernel identifier; (d) access a second registry to obtain a context state base address; (e) determine a context state address from the context state base address and the kernel identifier; (f) use a context mask at the context mask address to determine corresponding active context state; and (g) load the corresponding active context state into the coarse-grained reconfigurable array processor.
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公开(公告)号：US20240111538A1
公开(公告)日：2024-04-04
申请号：US18524942
申请日：2023-11-30
Applicant: Micron Technology, Inc.
Inventor： Douglas Vanesko , Tony M. Brewer
CPC classification number: G06F9/325 , G06F9/3867
Abstract: Disclosed in some examples, are methods, systems, devices, and machine-readable mediums which provide for more efficient CGRA execution by assigning different initiation intervals to different PEs executing a same code base. The initiation intervals may be a multiple of each other and the PE with the lowest initiation interval may be used to execute instructions of the code that is to be executed at a greater frequency than other instructions than other instructions that may be assigned to PEs with higher initiation intervals.
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公开(公告)号：US20230055320A1
公开(公告)日：2023-02-23
申请号：US17402849
申请日：2021-08-16
Applicant: Micron Technology, Inc.
Inventor： Douglas Vanesko , Bryan Hornung
Abstract: Various examples are directed to systems and methods for performing operations in a reconfigurable compute fabric. A dispatch interface may send a first asynchronous message to a first flow controller of a first synchronous flow. The first asynchronous message may instruct the first flow controller to begin execution of a first-level loop. The first synchronous flow may send a second asynchronous message to a second flow controller of a second synchronous flow. The second asynchronous message may instruct the second flow controller to execute a second-level loop. The first flow controller may receive a third asynchronous message indicating that the second-level loop has completed and that a synchronous flow thread is free for executing a next iteration of the first-level loop.
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Patent Agency Ranking
公开(公告)号：US20230051544A1
公开(公告)日：2023-02-16
申请号：US17399801
申请日：2021-08-11
Applicant: Micron Technology, Inc.
Inventor： Douglas Vanesko , Tony M. Brewer
Abstract: Disclosed in some examples, are methods, systems, devices, and machine-readable mediums which provide for more efficient CGRA execution by assigning different initiation intervals to different PEs executing a same code base. The initiation intervals may be a multiple of each other and the PE with the lowest initiation interval may be used to execute instructions of the code that is to be executed at a greater frequency than other instructions than other instructions that may be assigned to PEs with higher initiation intervals.
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公开(公告)号：US20230050687A1
公开(公告)日：2023-02-16
申请号：US17402840
申请日：2021-08-16
Applicant: Micron Technology, Inc.
Inventor： Bryan Hornung , Douglas Vanesko
Abstract: Various examples are directed to systems and methods in which a first flow controller of a first synchronous flow may receive an instruction to execute a first loop using the first synchronous flow. The first flow controller may determine a first iteration index for a first iteration of the first loop. The first flow controller may send, to a first compute element of the first synchronous flow, a first synchronous message to initiate a first synchronous flow thread for executing the first iteration of the first loop. The first synchronous message may comprise the iteration index. The first compute element may execute an input/output operation at a first location of a first compute element memory indicated by the first iteration index.
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公开(公告)号：US20220317283A1
公开(公告)日：2022-10-06
申请号：US17240548
申请日：2021-04-26
Applicant: Micron Technology, Inc.
Inventor： Patrick Estep , Tony M. Brewer , Bryan Hornung , Douglas Vanesko
IPC: G01S13/90 , G06F12/0815
Abstract: A synthetic-aperture radar (SAR) antenna emits radar pulses and receives their reflections. SAR is typically used on a moving platform, such as an aircraft, drone, or spacecraft. Since the position of the antenna changes between the time of emitting a radar pulse and receiving the reflection of the pulse, the synthetic aperture of the radar is increased, giving greater accuracy for a same (physical) sized radar over conventional beam-scanning radar. The pulse data is processed, using a backprojection algorithm, to generate a two-dimensional image that can be used for navigation. The order in which the SAR data is processed can impact the likelihood of cache hits in accessing the data. Since accessing data from cache instead of memory storage reduces both access time and power consumption, devices that access more data from cache have greater battery life and range.
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公开(公告)号：US20240070112A1
公开(公告)日：2024-02-29
申请号：US17899714
申请日：2022-08-31
Applicant: Micron Technology, Inc.
Inventor： Bryan Hornung , Douglas Vanesko , David Patrick
CPC classification number: G06F15/80 , G06F9/30018
Abstract: Devices and techniques for loading contexts in a coarse-grained reconfigurable array processor are described herein. A system or apparatus may include context load circuitry operable to load context for a coarse-grained reconfigurable array processor, where the context load circuitry is configured to: (a) receive a kernel identifier; (b) access a first registry to obtain a context mask base address; (c) determine a context mask address from the context mask base address and the kernel identifier; (d) access a second registry to obtain a context state base address; (e) determine a context state address from the context state base address and the kernel identifier; (f) use a context mask at the context mask address to determine corresponding active context state; and (g) load the corresponding active context state into the coarse-grained reconfigurable array processor.
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公开(公告)号：US11789642B2
公开(公告)日：2023-10-17
申请号：US17360455
申请日：2021-06-28
Applicant: Micron Technology, Inc.
Inventor： Douglas Vanesko , Bryan Hornung , Tony M. Brewer
CPC classification number: G06F3/0655 , G06F3/0622 , G06F3/0679
Abstract: A dispatch element interfaces with a host processor and dispatches threads to one or more tiles of a hybrid threading fabric. Data structures in memory to be used by a tile may be identified by a starting address and a size, included as parameters provided by the host. The dispatch element sends a command to a memory interface to transfer the identified data to the tile that will use the data. Thus, when the tile begins processing the thread, the data is already available in local memory of the tile and does not need to be accessed from the memory controller. Data may be transferred by the dispatch element while the tile is performing operations for another thread, increasing the percentage of operations performed by the tile that are performing useful work and reducing the percentage that are merely retrieving data.
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