-
公开(公告)号：US08509264B2
公开(公告)日：2013-08-13
申请号：US13466236
申请日：2012-05-08
IPC分类号： H04J3/24
CPC分类号： H04L47/34 , H04B7/2603 , H04L1/1812 , H04L47/14 , H04L49/90 , H04L49/901 , H04L49/9094 , H04W80/02
摘要： A radio receiving apparatus for receiving the variable-length RLC PDU data in an RLC layer includes the buffer memory sectioned into a plurality of areas having a predetermined maximum data length of the RLC PDU data. By referring to a sequence number SN included in each received RLC PDU data, the radio receiving apparatus stores the RLC PDU data having an identical sequence number SN into an identical area, and assembles an RLC SDU data on a basis of the RLC PDU data stored in each area.
摘要翻译： 一种用于在RLC层中接收可变长度RLC PDU数据的无线电接收装置包括被分成具有RLC PDU数据的预定最大数据长度的多个区域的缓冲存储器。 通过参照包含在每个接收的RLC PDU数据中的序列号SN，无线电接收装置将具有相同序列号SN的RLC PDU数据存储到相同区域中，并且基于存储的RLC PDU数据来组合RLC SDU数据 在每个地区。
-
公开(公告)号：US20110255477A1
公开(公告)日：2011-10-20
申请号：US13171664
申请日：2011-06-29
IPC分类号： H04W4/00
CPC分类号： H04L47/34 , H04B7/2603 , H04L1/1812 , H04L47/14 , H04L49/90 , H04L49/901 , H04L49/9094 , H04W80/02
摘要： A radio receiving apparatus for receiving the variable-length RLC PDU data in an RLC layer includes the buffer memory sectioned into a plurality of areas having a predetermined maximum data length of the RLC PDU data. By referring to a sequence number SN included in each received RLC PDU data, the radio receiving apparatus stores the RLC PDU data having an identical sequence number SN into an identical area, and assembles an RLC SDU data on a basis of the RLC PDU data stored in each area.
摘要翻译： 一种用于在RLC层中接收可变长度RLC PDU数据的无线电接收装置包括被分成具有RLC PDU数据的预定最大数据长度的多个区域的缓冲存储器。 通过参照包含在每个接收的RLC PDU数据中的序列号SN，无线电接收装置将具有相同序列号SN的RLC PDU数据存储到相同区域中，并且基于存储的RLC PDU数据来组合RLC SDU数据 在每个地区。
-
公开(公告)号：US08000348B2
公开(公告)日：2011-08-16
申请号：US11889833
申请日：2007-08-16
IPC分类号： H04J3/00
CPC分类号： H04L47/34 , H04B7/2603 , H04L1/1812 , H04L47/14 , H04L49/90 , H04L49/901 , H04L49/9094 , H04W80/02
摘要： A radio receiving apparatus for receiving the variable-length RLC PDU data in an RLC layer includes the buffer memory sectioned into a plurality of areas having a predetermined maximum data length of the RLC PDU data. By referring to a sequence number SN included in each received RLC PDU data, the radio receiving apparatus stores the RLC PDU data having an identical sequence number SN into an identical area, and assembles an RLC SDU data on a basis of the RLC PDU data stored in each area.
摘要翻译： 一种用于在RLC层中接收可变长度RLC PDU数据的无线电接收装置包括被分成具有RLC PDU数据的预定最大数据长度的多个区域的缓冲存储器。 通过参照包含在每个接收的RLC PDU数据中的序列号SN，无线电接收装置将具有相同序列号SN的RLC PDU数据存储到相同区域中，并且基于存储的RLC PDU数据来组合RLC SDU数据 在每个地区。
-
公开(公告)号：US20080043652A1
公开(公告)日：2008-02-21
申请号：US11889833
申请日：2007-08-16
IPC分类号： H04B7/00
CPC分类号： H04L47/34 , H04B7/2603 , H04L1/1812 , H04L47/14 , H04L49/90 , H04L49/901 , H04L49/9094 , H04W80/02
摘要： A radio receiving apparatus for receiving the variable-length RLC PDU data in an RLC layer includes the buffer memory sectioned into a plurality of areas having a predetermined maximum data length of the RLC PDU data. By referring to a sequence number SN included in each received RLC PDU data, the radio receiving apparatus stores the RLC PDU data having an identical sequence number SN into an identical area, and assembles an RLC SDU data on a basis of the RLC PDU data stored in each area.
摘要翻译： 一种用于在RLC层中接收可变长度RLC PDU数据的无线电接收装置包括被分成具有RLC PDU数据的预定最大数据长度的多个区域的缓冲存储器。 通过参照包含在每个接收的RLC PDU数据中的序列号SN，无线电接收装置将具有相同序列号SN的RLC PDU数据存储到相同区域中，并且基于存储的RLC PDU数据来组合RLC SDU数据 在每个地区。
-
35.发明授权Logic circuit redesign program, logic circuit redesign apparatus, and logic circuit redesign method 失效逻辑电路重新设计程序，逻辑电路重新设计装置和逻辑电路重新设计方法公开(公告)号：US07735028B2
公开(公告)日：2010-06-08
申请号：US11902050
申请日：2007-09-18
申请人： Yoshinori Soejima , Yoshikatsu Kouhara , Hiroaki Shiraishi , Kouichi Tanda , Takakazu Tokunaga , Koji Takatomi
发明人： Yoshinori Soejima , Yoshikatsu Kouhara , Hiroaki Shiraishi , Kouichi Tanda , Takakazu Tokunaga , Koji Takatomi
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A computer is allowed to execute an information acquisition process that acquires a file expressing information on pins used in respective ports provided in each block of a logic circuit to be redesigned and information indicating connection relationships between the ports (#2); execute a multiplexer disposition process that, based on the file, classifies pins of output ports of a block into a number of pin groups that is less than the number of pins, and disposes a multiplexer having a function to multiplex a signal output from each pin classified in the same pin group (#11, #13); and execute a demultiplexer disposition process that, based on that file, disposes a demultiplexer having a function to demultiplex signals that have been output from output ports of a block and multiplexed by the multiplexer, and a function to output each demultiplexed signal to input ports of respective input destination blocks (#12, #13).
摘要翻译： 允许计算机执行信息获取处理，获取表示在要重新设计的逻辑电路的每个块中提供的相应端口中使用的引脚的信息的文件和指示端口之间的连接关系的信息（＃2）。 执行多路复用器配置处理，其基于该文件，将块的输出端口的引脚分成小于引脚数的多个引脚组，并且配置具有复用从每个引脚输出的信号的功能的多路复用器 分为同一个针脚组（＃11，＃13）; 并且执行解复用器配置处理，其基于该文件，配置具有从多路复用器的多路复用器的多路复用器多路复用的多路复用器的输出端口输出的多路复用功能的解复用器，以及将各解复用信号输出到 各个输入目的地块（＃12，＃13）。
-
公开(公告)号：US06201488B1
公开(公告)日：2001-03-13
申请号：US09257788
申请日：1999-02-25
申请人： Teruyuki Sato , Hideaki Kurihara , Yoshinori Soejima , Yasuko Shirai , Masato Ito , Kazuhiro Nomoto
发明人： Teruyuki Sato , Hideaki Kurihara , Yoshinori Soejima , Yasuko Shirai , Masato Ito , Kazuhiro Nomoto
IPC分类号： H03M700
CPC分类号： G06F9/445 , G06F9/24 , G06F9/32 , G06F9/3802 , G06F9/3804 , G06F9/3814
摘要： A CODEC has a DSP which can consecutively execute a plurality of algorithms without restriction of a memory capacity. The DSP performs an encoding/decoding operation on a digital signal. A program memory stores a program divided into a plurality of block programs, the program being stored on an individual block program basis. A data memory stores a set of data used for executing each block program stored in the program memory, the set of data being divided into a plurality of data blocks and stored on an individual data block basis. A program executing unit executes each block program stored in the program memory by using a corresponding data block stored in the data memory. A program changing unit obtains a new block program from an external device each time execution of one of the block programs by the program executing unit is completed so as to store the obtained new block program in the program memory.
摘要翻译： CODEC具有DSP，其可以连续执行多个算法而不限制存储器容量。 DSP对数字信号执行编码/解码操作。 程序存储器存储被划分为多个块程序的程序，该程序以各个块程序为基础存储。 数据存储器存储用于执行存储在程序存储器中的每个块程序的一组数据，该组数据被划分为多个数据块并且以单个数据块为基础存储。 程序执行单元通过使用存储在数据存储器中的相应数据块来执行存储在程序存储器中的每个块程序。 程序改变单元每当程序执行单元执行一个块程序完成时，从外部设备获得新的程序块，以便将获得的新程序块存储在程序存储器中。
-
公开(公告)号：US20070217444A1
公开(公告)日：2007-09-20
申请号：US11711806
申请日：2007-02-28
IPC分类号： H04L12/66
CPC分类号： G06F17/5045
摘要： A computer capable of easily obtaining RTL of a TOP circuit after a block circuit is separated out of the TOP circuit. A port information input unit inputs the port information of the TOP circuit described in RTL, and the port information of block circuits composing the TOP circuit, from a user. A separation information input unit inputs separation information specifying a block circuit to be separated out of the TOP circuit, from the user. A separation port information creation unit creates separation port information after the block circuit is separated, by changing the port information of the TOP circuit and the block circuits based on the port information of the block circuit to be separated according to the separation information. An RTL rewriting unit rewrites RTL of the TOP circuit from which the block circuit has been separated, based on the separation port information created by the separation port information creation unit.
摘要翻译： 能够在块电路之后容易地获得TOP电路的RTL的计算机从TOP电路分离出来。 端口信息输入单元从用户输入RTL中描述的TOP电路的端口信息和构成TOP电路的块电路的端口信息。 分离信息输入单元从用户输入指定要从TOP电路分离的块电路的分离信息。 分离端口信息创建单元通过根据分离信息根据要分离的块电路的端口信息改变TOP电路和块电路的端口信息，在块电路分离之后创建分离端口信息。 RTL重写单元基于由分离端口信息创建单元创建的分离端口信息重写已经从块电路分离的TOP电路的RTL。
-
38.发明申请Logic circuit redesign program, logic circuit redesign apparatus, and logic circuit redesign method 失效逻辑电路重新设计程序，逻辑电路重新设计装置和逻辑电路重新设计方法公开(公告)号：US20080077904A1
公开(公告)日：2008-03-27
申请号：US11902050
申请日：2007-09-18
申请人： Yoshinori Soejima , Yoshikatsu Kouhara , Hiroaki Shiraishi , Kouichi Tanda , Takakazu Tokunaga , Koji Takatomi
发明人： Yoshinori Soejima , Yoshikatsu Kouhara , Hiroaki Shiraishi , Kouichi Tanda , Takakazu Tokunaga , Koji Takatomi
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A computer is allowed to execute an information acquisition process that acquires a file expressing information on pins used in respective ports provided in each block of a logic circuit to be redesigned and information indicating connection relationships between the ports (#2); execute a multiplexer disposition process that, based on the file, classifies pins of output ports of a block into a number of pin groups that is less than the number of pins, and disposes a multiplexer having a function to multiplex a signal output from each pin classified in the same pin group (#11, #13); and execute a demultiplexer disposition process that, based on that file, disposes a demultiplexer having a function to demultiplex signals that have been output from output ports of a block and multiplexed by the multiplexer, and a function to output each demultiplexed signal to input ports of respective input destination blocks (#12, #13).
摘要翻译： 允许计算机执行信息获取处理，获取表示在要重新设计的逻辑电路的每个块中提供的相应端口中使用的引脚的信息的文件和指示端口之间的连接关系的信息（＃2）。 执行多路复用器配置处理，其基于该文件，将块的输出端口的引脚分成小于引脚数的多个引脚组，并且配置具有复用从每个引脚输出的信号的功能的多路复用器 分为同一个针脚组（＃11，＃13）; 并且执行解复用器配置处理，其基于该文件，配置具有对多路复用器的多路复用器多路复用的多路复用器的输出端口输出的信号进行解复用的解复用器，以及将各解复用信号输出到 各个输入目的地块（＃12，＃13）。
-
-
-
-
-
-
-
搜索结果
38 条记录 (耗时 0.03 秒)
