公开(公告)号：US6030862A

公开(公告)日：2000-02-29

申请号：US170060

申请日：1998-10-13

申请人： Nick Kepler

发明人： Nick Kepler

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857

摘要： Sharply-defined dopant profiles in the transistor channel region of ultra high density semiconductor devices are maintained by selective transistor channel implants to reduce exposure to heat cycling, thereby reducing dopant diffusion. Embodiments include forming isolation regions on a semiconductor substrate, forming a relatively thick first gate dielectric layer, then performing transistor channel implantations. The first gate dielectric layer is then masked and etched, and a second, thinner gate dielectric layer is formed. The transistor channel implants are not affected by the temperature cycle of the first gate dielectric layer formation, thereby enabling dual gate dielectric formation without adversely affecting the electrical characteristics of the finished device.

摘要翻译： 在超高密度半导体器件的晶体管沟道区域中，通过选择性晶体管沟道注入来维持明确定义的掺杂物分布，以减少暴露于热循环，从而减少掺杂剂扩散。 实施例包括在半导体衬底上形成隔离区域，形成相对较厚的第一栅极电介质层，然后执行晶体管沟道注入。 然后对第一栅极介电层进行掩模蚀刻，形成第二较薄的栅介质层。 晶体管沟道植入物不受第一栅极介电层形成的温度循环的影响，从而实现双栅电介质形成而不会不利地影响最终器件的电特性。