公开(公告)号：US06171962B2

公开(公告)日：2001-01-09

申请号：US08993889

申请日：1997-12-18

申请人： Olov Karlsson ,  Christopher F. Lyons ,  Basab Bandyopadhyay ,  Nick Kepler ,  Larry Wang ,  Effiong Ibok

发明人： Olov Karlsson ,  Christopher F. Lyons ,  Basab Bandyopadhyay ,  Nick Kepler ,  Larry Wang ,  Effiong Ibok

IPC分类号： H01L21302

CPC分类号： H01L21/76229 ,  H01L21/31053

摘要： An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate without a planarization mask or etch. Embodiments include forming trenches and refilling them with an insulating material which also covers the substrate surface, followed by polishing to remove an upper portion of the insulating material and to planarize the insulating material above the small trenches. A second layer of insulating material is then deposited to fill seams in the insulating material above the small trenches and to fill steps in the insulating material above the large trenches. The insulating material is then planarized. Since the insulating material is partially planarized by the first polish and the seams and steps are filled by the second deposition, the resulting topography of the upper surface of the second layer of insulating material is small enough to enable a direct final polish without the need to create and implement a planarization mask and to perform an etch and mask removal, thereby reducing manufacturing costs and increasing production throughput.

摘要翻译： 在半导体衬底中形成具有不同宽度的大的和小的沟槽的绝缘沟槽隔离结构，而不需要平坦化掩模或蚀刻。 实施例包括用绝缘材料形成沟槽并再填充它们，该绝缘材料也覆盖衬底表面，接着进行抛光以除去绝缘材料的上部并使小沟槽上方的绝缘材料平坦化。 然后沉积第二层绝缘材料以填充小沟槽上方的绝缘材料中的接缝，并填充大沟槽上方的绝缘材料的步骤。 然后将绝缘材料平坦化。 由于绝缘材料被第一抛光部分地平坦化并且接缝和步骤通过第二次沉积来填充，所以第二层绝缘材料的上表面的所得形貌足够小以使得能够进行直接的最终抛光，而不需要 创建并实现平面化掩模并执行蚀刻和掩模去除，从而降低制造成本并提高生产量。

公开(公告)号：US6130467A

公开(公告)日：2000-10-10

申请号：US993857

申请日：1997-12-18

申请人： Basab Bandyopadhyay ,  Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Effiong Ibok ,  Christopher F. Lyons

发明人： Basab Bandyopadhyay ,  Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Effiong Ibok ,  Christopher F. Lyons

IPC分类号： H01L21/762 ,  H01L29/00

CPC分类号： H01L21/76224

摘要： An insulated trench isolation structure is formed in a semiconductor substrate with an oxide or nitride spacer overlying and protecting a portion of a pad oxide layer at the trench edge such that the pad oxide layer acts as part of the gate oxide layer. Embodiments include providing a step between the trench fill and the pad oxide layer and forming the protective spacer thereon. The protective spacer protects the underlying portion of the pad oxide layer at the trench edge during pad oxide removal prior to forming a gate oxide. Therefore, it is only necessary to grow the gate oxide on the main surface of the substrate, not at the trench edges. The gate oxide can then be formed uniformly thin, while the remaining pad oxide at the trench edges is relatively thick.

摘要翻译： 在具有氧化物或氮化物间隔物的半导体衬底中形成绝缘沟槽隔离结构，覆盖并保护沟槽边缘处的焊盘氧化物层的一部分，使得焊盘氧化物层用作栅极氧化物层的一部分。 实施例包括在沟槽填充物和衬垫氧化物层之间提供步骤，并在其上形成保护隔离物。 在形成栅极氧化物之前，保护间隔物在衬垫氧化物去除期间保护焊盘氧化物层的沟槽边缘的下面部分。 因此，仅需要在衬底的主表面上而不是在沟槽边缘处生长栅极氧化物。 然后可以将栅极氧化物均匀地形成，而沟槽边缘处的剩余焊盘氧化物相对较厚。

公开(公告)号：US6090713A

公开(公告)日：2000-07-18

申请号：US992491

申请日：1997-12-18

申请人： Olov Karlsson ,  Christopher F. Lyons ,  Basab Bandyophadhyay ,  Nick Kepler ,  Larry Wang ,  Effiong Ibok

发明人： Olov Karlsson ,  Christopher F. Lyons ,  Basab Bandyophadhyay ,  Nick Kepler ,  Larry Wang ,  Effiong Ibok

IPC分类号： H01L21/3105 ,  H01L21/762 ,  H01L21/316

CPC分类号： H01L21/76229 ,  H01L21/31053 ,  H01L21/31055

摘要： An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate using a simplified reverse source/drain planarization mask. Embodiments include forming trenches and refilling them with an insulating material which also covers the substrate surface, polishing to remove an upper portion of the insulating material and to planarize the insulating material above the small trenches, depositing a second, thin layer of insulating material filling seams in the insulating material above the small trenches, masking the insulating material above the large trenches, isotropically etching, and polishing to planarize the insulating material. Since the insulating material is partially planarized and the seams over the small trenches are filled, etching can be carried out after the formation of a relatively simple planarization mask over only the large trenches, and not the small trenches. The use of a planarization mask having relatively few features with relatively large geometry avoids the necessity of creating and implementing a complex, critical mask, thereby reducing manufacturing costs and increasing production throughput.

摘要翻译： 使用简化的反向源极/漏极平面化掩模在半导体衬底中形成具有不同宽度的大的和小的沟槽的绝缘沟槽隔离结构。 实施例包括形成沟槽并用也覆盖衬底表面的绝缘材料再填充它们，抛光以去除绝缘材料的上部并平面化小沟槽上方的绝缘材料，沉积第二薄层的绝缘材料填充接缝 在小沟槽上方的绝缘材料中，掩蔽大沟槽上方的绝缘材料，各向同性蚀刻和抛光以使绝缘材料平坦化。 由于绝缘材料被部分平坦化并且填充了小沟槽上的接缝，所以可以在仅在大沟槽而不是小沟槽上形成相对简单的平坦化掩模之后进行蚀刻。 使用具有相对较小几何特征的平面化掩模具有相对大的几何形状避免了创建和实施复杂的关键掩模的必要性，从而降低制造成本并提高生产量。

公开(公告)号：US5930645A

公开(公告)日：1999-07-27

申请号：US993881

申请日：1997-12-18

申请人： Christopher F. Lyons ,  Basab Bandyopadhyay ,  Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Effiong Ibok

发明人： Christopher F. Lyons ,  Basab Bandyopadhyay ,  Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Effiong Ibok

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76232

摘要： An insulated trench isolation structure is formed in a semiconductor substrate using a thin amorphous silicon or polysilicon polish stop layer by adding a reflectance compensation layer on the polish stop layer. As a result, the topological step between the main surface of the substrate and the uppermost surface of the trench fill is reduced, thereby facilitating the application and enhancing the accuracy of photolithographic techniques in forming features with minimal dimensions.

摘要翻译： 通过在抛光停止层上添加反射率补偿层，在半导体衬底中使用薄的非晶硅或多晶硅抛光停止层形成绝缘沟槽隔离结构。 结果，衬底的主表面和沟槽填充物的最上表面之间的拓扑步骤减少，从而有助于在最小尺寸形成特征时光刻技术的应用和提高精度。

公开(公告)号：US5795820A

公开(公告)日：1998-08-18

申请号：US673005

申请日：1996-07-01

申请人： Nick Kepler

发明人： Nick Kepler

IPC分类号： H01L21/768 ,  H01L21/441

CPC分类号： H01L21/76801 ,  H01L21/76834 ,  H01L21/76895

摘要： A method and apparatus is provided for simplifying the manufacture of an interlayer dielectric where local interconnects are utilized. The invention utilizes a separate LI stack and first contact stack deposition and etch. In the first step, a layer of oxide etch stop and a layer of TEOS oxide are deposited to form a first LI stack. This stack is then contact etched, filled, and polished. A first contact stack is then formed by deposition of a doped silane oxide layer that is contact etched, filled, and polished. The method produces an ILD with a first layer of oxide etch stop, a second layer of undoped TEOS oxide, and a final layer of doped silane oxide.

摘要翻译： 提供了一种用于简化使用局部互连的层间电介质的制造的方法和装置。 本发明利用单独的LI堆叠和第一接触堆叠沉积和蚀刻。 在第一步骤中，沉积一层氧化物蚀刻停止层和一层TEOS氧化物以形成第一个LI堆叠。 然后将该叠层接触刻蚀，填充和抛光。 然后通过沉积接触蚀刻，填充和抛光的掺杂硅烷氧化物层形成第一接触堆叠。 该方法产生具有第一层氧化物蚀刻停止层的第一层，未掺杂的TEOS氧化物层的第二层和掺杂的硅烷氧化物的最终层。

公开(公告)号：US06239031B1

公开(公告)日：2001-05-29

申请号：US09487493

申请日：2000-01-19

申请人： Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Basab Bandyopadhyah ,  Effiong Ibok ,  Christopher F. Lyons

发明人： Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Basab Bandyopadhyah ,  Effiong Ibok ,  Christopher F. Lyons

IPC分类号： H01L21302

CPC分类号： G03F9/7076 ,  G03F9/70 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

摘要： Accurate photolighographic processing is achieved employing a stepper global alignment structure enabling formation thereon of a substantially transparent layer having a substantially planar upper surface. Embodiments include a set of global alignment marks comprising spaced apart trenches, each trench segmented into a plurality of narrow trenches spaced apart by uprights and forming a dummy topographical area of narrow trenches surrounding the set of alignment marks. The segmented trenches and the dummy topographical area effectively provide a substantially uniform topography enabling deposition of a transparent layer without steps and effective local planarization. Since the upper surface of the transparent layer is substantially planar, layers of material deposited on the transparent layer during subsequent processing also have a substantially planar upper surface, thereby enabling transmission of the signal produced by the alignment marks to the stepper with minimal distortion.

摘要翻译： 使用步进全局对准结构可实现准确的视差处理，该结构能够在其上形成具有基本平坦的上表面的基本透明的层。 实施例包括一组包括间隔开的沟槽的全局对准标记，每个沟槽被分段成由立柱间隔开的多个窄沟槽，并形成围绕该组对准标记的窄沟槽的虚拟地形区域。 分段沟槽和虚拟地形区域有效地提供基本均匀的形貌，使得能够沉积透明层而无需步骤和有效的局部平面化。 由于透明层的上表面基本上是平面的，因此在随后的处理期间沉积在透明层上的材料层也具有基本平坦的上表面，从而能够以最小的变形将由对准标记产生的信号传输到步进机。

公开(公告)号：US06204177B1

公开(公告)日：2001-03-20

申请号：US09185515

申请日：1998-11-04

申请人： Paul R. Besser ,  Nick Kepler ,  Karsten Wieczorek

发明人： Paul R. Besser ,  Nick Kepler ,  Karsten Wieczorek

IPC分类号： H01L2144

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L29/456 ,  H01L29/4933

摘要： A method of forming metal silicide in a semiconductor wafer with reduced junction leakage introduces an alloy at cobalt grain boundaries within a cobalt layer that overlays a silicon layer. The alloy element can be precipitated during deposition of the cobalt and the alloy element, or by an intermediate anneal after deposition. The cobalt layer and the silicon layer are then annealed to form metal silicide regions. By precipitating an alloy at the cobalt grain boundaries, cobalt diffusion at the grain boundaries is retarded during a first rapid thermal annealing step. Bulk diffusion is encouraged, and a more uniform silicide film with reduced interface roughness is produced. Since the interface roughness is reduced with the methods of the present invention, junction leakage is reduced. This allows shallower junctions to be fabricated, leading to devices with improved performance.

摘要翻译： 在具有减少的结漏电的半导体晶片中形成金属硅化物的方法在覆盖硅层的钴层内的钴晶界处引入合金。 在钴和合金元素的沉积期间，或者通过沉积后的中间退火，合金元素可以沉淀。 然后将钴层和硅层退火以形成金属硅化物区域。 通过在钴晶界析出合金，在第一快速热退火步骤期间，在晶界处的钴扩散被延迟。 鼓励扩散，并产生具有降低的界面粗糙度的更均匀的硅化物膜。 由于通过本发明的方法减小了界面粗糙度，所以结漏电减少。 这允许制造较浅的结，导致具有改进性能的器件。

公开(公告)号：US6165903A

公开(公告)日：2000-12-26

申请号：US185516

申请日：1998-11-04

申请人： Paul R. Besser ,  Nick Kepler ,  Karsten Wieczorek

发明人： Paul R. Besser ,  Nick Kepler ,  Karsten Wieczorek

IPC分类号： H01L21/285 ,  H01L21/44

CPC分类号： H01L21/28525 ,  H01L21/28518

摘要： A method for forming ultra shallow junctions in a semiconductor wafer with reduced silicon consumption during salicidation supplies additional silicon during the salicidation process. After the gate and source/drain junctions are formed in a semiconductor device, high resistivity metal silicide regions are formed on the gate and source/drain junctions. Silicon is then deposited in a layer on the high resistivity metal silicide regions. An annealing step is then performed to form low resistivity metal silicide regions on the gate and source/drain junctions. The deposited silicon is a source of silicon that is employed as a diffusion species during the transformation of the high resistivity metal silicide (such as CoSi) to a low resistivity metal silicide (such as CoSi.sub.2). Since the additional silicon provided in the deposited layer is consumed, there is reduced consumption of the silicon from the ultra-shallow junctions, thereby preventing the bottom of the silicide regions from reaching the bottom of the source/drain junctions.

摘要翻译： 用于在半衰期期间形成超浅结的方法，其中在硅化过程中硅消耗减少，在硫化过程中提供额外的硅。 在半导体器件中形成栅极和源极/漏极结之后，在栅极和源极/漏极结上形成高电阻金属硅化物区域。 然后将硅沉积在高电阻率金属硅化物区域上的层中。 然后执行退火步骤以在栅极和源极/漏极结上形成低电阻率金属硅化物区域。 沉积的硅是在将高电阻率金属硅化物（例如CoSi）转变成低电阻率金属硅化物（例如CoSi 2）期间用作扩散物质的硅源。 由于在沉积层中提供的附加硅被消耗，所以硅从超浅结的消耗减少，从而防止硅化物区的底部到达源极/漏极结的底部。

公开(公告)号：US6162689A

公开(公告)日：2000-12-19

申请号：US187231

申请日：1998-11-06

申请人： Nick Kepler ,  Karsten Wieczorek ,  Larry Wang ,  Paul Raymond Besser

发明人： Nick Kepler ,  Karsten Wieczorek ,  Larry Wang ,  Paul Raymond Besser

IPC分类号： H01L21/266 ,  H01L21/285 ,  H01L21/336 ,  H01L29/417

CPC分类号： H01L29/66598 ,  H01L21/266 ,  H01L21/28518 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

摘要： High integrity ultra-shallow source/drain junctions are formed employing cobalt silicide contacts. Emdodiments include forming field oxide regions, gates, spacers, and lightly doped implants, and then depositing a layer of oxide on a substrate. The oxide layer is masked to protect portions of the oxide layer located near the gate, where it is desired to have a shallow junction, then etched to expose portions of the intended source/drain regions where the silicided contacts are to be formed. A high-dosage source/drain implant is thereafter carried out to form deep source/drain junctions with the substrate where the oxide layer has been etched away, and to form shallower junctions near the gates, where the implant must travel through the oxide layer before reaching the substrate. A layer of cobalt is thereafter deposited and silicidation is performed to form metal silicide contacts over only the deep source/drain junctions, while the cobalt on the oxide layer (i.e., above the shallower junctions) does not react to form cobalt silicide, and is thereafter removed. The present invention provides ultra-shallow source-drain junctions near the gates for improved electrical characteristics, and deeper junctions away from the gates, with cobalt silicide contacts above only the deeper junction portions to avoid junction leakage, thereby facilitating reliable device scaling.

摘要翻译： 使用硅化钴接触形成高完整性超浅源极/漏极结。 实例包括形成场氧化物区域，栅极，间隔物和轻掺杂的植入物，然后在衬底上沉积氧化物层。 掩模氧化层以保护位于栅极附近的氧化物层的部分，期望具有浅结，然后蚀刻以暴露要形成硅化物触点的预期源/漏区的部分。 此后，进行高剂量源/漏注入，以与氧化物层被蚀刻掉的衬底形成深的源极/漏极结，并且在栅极附近形成较浅的结，其中植入物必须在 到达基板。 此后沉积一层钴，并且仅在深源极/漏极接合处进行硅化以形成金属硅化物接触，而氧化物层上的钴（即，较浅的接合点上方）不反应形成硅化钴，并且是 此后取出。 本发明提供了栅极附近的超浅源极 - 漏极结，用于改善电气特性，以及远离栅极的较深的结，钴硅化物接触仅在较深的接合部分上方，以避免结漏电，从而便于可靠的器件缩放。

公开(公告)号：US6096599A

公开(公告)日：2000-08-01

申请号：US187521

申请日：1998-11-06

申请人： Nick Kepler ,  Karsten Wieczorek ,  Larry Wang ,  Paul Raymond Besser

发明人： Nick Kepler ,  Karsten Wieczorek ,  Larry Wang ,  Paul Raymond Besser

IPC分类号： H01L21/225 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8242

CPC分类号： H01L29/66575 ,  H01L21/2257 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/665 ,  Y10S438/923

摘要： High integrity shallow source/drain junctions are formed employing cobalt silicide contacts. Embodiments include depositing a layer of cobalt on a substrate above intended source/drain regions, depositing a cap layer of titanium or titanium nitride on the cobalt, depositing a doped film on the cap layer, and performing silicidation, as by rapid thermal annealing, to form a low-resistivity cobalt silicide and to diffuse impurities from the doped film through the cobalt silicide into the substrate to form a junction extending into the substrate a constant depth below the cobalt silicide interface. The formation of source/drain junctions self-aligned to the cobalt silicide/silicon interface prevents junction leakage while allowing the formation of cobalt silicide contacts at optimum thickness, thereby facilitating reliable device scaling.

摘要翻译： 使用硅化钴接触形成高度完整的浅源极/漏极结。 实施例包括在目标源极/漏极区域上的衬底上沉积钴层，在钴上沉积钛或氮化钛的覆盖层，在覆盖层上沉积掺杂的膜，并通过快速热退火进行硅化， 形成低电阻率的硅化钴，并且通过硅化钴将掺杂的膜中的杂质扩散到衬底中，以形成在硅化钴界面下面延伸到衬底中的恒定深度的结。 与硅化钴/硅界面自对准的源极/漏极结的形成防止结漏，同时允许在最佳厚度下形成硅化钴触点，从而便于可靠的器件缩放。